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C9531 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. C9531
Description  PCIX I/O System Clock Generator with EMI Control Features
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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C9531 Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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C9531
Document #: 38-07034 Rev. *D
Page 5 of 10
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state
condition by bringing their relevant OE pins to a logic low state.
This transition to and from a three-state and active condition
is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus
control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
The output enable pin contains an internal pull-up resistor that
will insure that a logic 1 is maintained and sensed by the
device if no external circuitry is connected to this pin.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 bits 3 and 4 to control
the output clock’s frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal.
where:
CXTAL
= The load rating of the crystal.
CXINFTG
= The clock generators XIN pin effective device internal capacitance to ground.
CXOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground.
CXINPCB
= The effective capacitance to ground of the crystal to device PCB trace.
CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace.
CXINDISC = Any discrete capacitance that is placed between the XIn pin and ground.
CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
As an example and using this formula for this data sheet’s
device, a design that has no discrete loading capacitors
(CDISC) and each of the crystal device PCB traces has a
capacitance (CPCB) to ground of 4 pF (typical value) would
calculate as:
Therefore, to obtain output frequencies that are as close to this
data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is
designed to work into a load of 20 pF.
(CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
CL =
C
XINPCB
C
XOUTPCB
C
XOUTDISC
C
XINDISC
C
XINFTG
C
XOUTFTG
XIN
XOUT
Clock Generator
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
CL =
40 x 40
40 x 40
=
=
1600
80
= 20 pF.


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