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TPS53647 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS53647 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 120 page  7 TPS53647 www.ti.com SLUSC39A – JUNE 2015 – REVISED JULY 2016 Product Folder Links: TPS53647 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 6.5 Electrical Characteristics over recommended free-air temperature range, VVIN = 12 V, VV5 = 5 V, VVSN = GND, VVSP = VOUT (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY: CURRENTS, UVLO, AND POWER-ON RESET IVIN VIN supply current, 4-phase active VVDAC < VVSP < VVDAC + 100 mV, ENABLE = HI 115 µA IV5 V5 supply current PMBus Idle, ENABLE = HI 6.1 7 mA IV5SBY V5 standby current ENABLE = LO 2 2.6 mA VV3R3 V3R3 output voltage IV3R3 = 0 A 3.2 3.3 3.4 V VV3R3(dropout) V3R3 load regulation IV3R3 = 5 mA 100 mV VV5UVLOH V5 UVLO OK threshold Ramp up 4.1 4.25 4.5 V VV5UVLOL V5 UVLO fault threshold Ramp down 3.95 4.05 4.25 V VHYS(V5) V5 UVLO hysteresis Hysteresis 0.15 0.23 0.3 V VVINUVLO VIN UVLO voltage MFR_SPEC_16[1:0] = 00 4.2 4.5 4.7 V MFR_SPEC_16[1:0] = 01 6.9 7.25 7.45 MFR_SPEC_16[1:0] = 10 8.6 9.0 9.25 MFR_SPEC_16[1:0] = 11 9.8 10.3 10.7 VHYS(VIN) VIN UVLO hysteresis voltage Hysteresis voltage 1 V REFERENCES: DAC AND VREF VVIDSTP VID Step size VR12.5: Change VID0 HI to LO to HI 10 mV VR12.0: Change VID0 HI to LO to HI 5 mV VDAC1 Closed Loop VSP tolerance VR12.0: 0.61 V ≤ VVSP ≤ 0.995 V, IOUT = 0 A , 0 °C ≤ TA≤ 85 °C –6 6.5 mV VDAC2 Closed Loop VSP tolerance VR12.0: 1 V ≤ VVSP ≤ 1.52 V, ICOUT = 0 A, 0 °C ≤ TA≤ 85 °C –0.6 0.6 % VDAC3 Closed Loop VSP tolerance VR12.5: 1.50V ≤ VVSP ≤ 2.50 V, IOUT = 0 A, 0 °C ≤ TA≤ 85 °C –1 1 % VDAC4 Closed Loop VSP tolerance VR12.0: 0.61 V ≤ VVSP ≤ 0.995 V, IOUT = 0 A, –40°C ≤ TA≤ 125 °C –8 8 mV VDAC5 Closed Loop VSP tolerance VR12.0: 1.0 V ≤ VVSP ≤ 1.52 V, IOUT = 0 A, –40 °C ≤ TA≤ 125 °C -0.8 0.8 % VDAC6 Closed Loop VSP tolerance VR12.5: 1.50 V ≤ VVSP ≤ 2.50V, IOUT = 0 A, –40°C ≤ TA≤ 125 °C -1.1 1.0 % VVREF VREF output 4.5 ≤ VV5 ≤ 5.5 V, IVREF = 0 A 1.685 1.70 1.717 V VVREFSRC VREF output source IVREF = 0 to 500 µA –4 -1 mV VVREFSNK VREF output sink IVREF = –500 to 0 µA 1 4 mV CURRENT SENSE: AMPLIFIER AND PHASE BALANCING GCSINT Internal current sense gain Gain from (CSPx – VREF ) to PWM comparator 1.0 V/V COMPENSATOR: VOLTAGE POSITIONING AND AMPLIFIER gM(isum) ISUM amplifier transconductance VVSP = 1.7 V 500 µS gM(comp) COMP amplifier transconductance VVSP = 1.7 V 1000 µS VCCLAMPN COMP amplifier negative clamp voltage (VVREF – VCOMP) VRAMP + 20 mV VCCLAMPP COMP amplifier positive clamp voltage (VCOMP – VVREF) 2.1 2.2 2.3 V VOLTAGE SENSE: VSP AND VSN IVSP VSP input bias current Not in fault, disable or UVLO, VVSP = VVDAC = 2.3 V, VVSN = 0 V 300 µA IVSN VSN input bias current Not in fault, disable or UVLO, VVSP = VVDAC = 2.3 V, VVSN = 0 V -30 -23 µA RSFTSTP Transistor resistance Connect to VSP 10 kΩ LOGIC ( RESET, VR_RDY, VR_FAULT, VR_HOT, AND ENABLE) INTERFACE PINS: I/O VOLTAGE AND CURRENT RRPGDL Open drain pull-down resistance VR_RDY, pulldown resistance at 0.31 V 36 50 Ω IVRTTLK Open drain leakage current VR_HOT, VR_RDY, hi-Z leakage, apply 3.3 V in off state –2 0.2 2 µA VRSTL RESET logic low RESET Pin 0.8 V VRSTH RESET logic high RESET Pin 1.2 V TRSTTDLY RESET Delay Time 1 µs VENL ENABLE logic low 0.3 V VENH ENABLE logic high 0.8 V IENH I/O 1.1- V leakage Leakage current , VENABLE = 1.1 V 25 µA PMBUS INTERFACE PINS: I/O VOLTAGE AND CURRENT VPMBL PMBus pins logic low 0.8 V VPMBH PMBus pins logic high 1.2 V IPMBL Logic low input current VPMBus=0 V -10 10 µA IPMBH Logic high input current VPMBus=1.8 V -10 10 µA |
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