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TPS544C25 Datasheet(PDF) 24 Page - Texas Instruments |
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TPS544C25 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 100 page  R RT = 2.01 × 10 10 f SW VOUT VSYNC/RESET_B (A) Pre-AVS VOUT Default VSET . (B) Time Response Delay 24 TPS544C25, TPS544B25 SLUSC81 – MAY 2015 www.ti.com Product Folder Links: TPS544C25 TPS544B25 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 7.3.7 Reset VOUT Without power cycling, the VOUT_COMMAND value and the corresponding output voltage can be reset to the default value set by VSET. To reset VOUT_COMMAND, the VSET pin should be used in combination with SYNC/RESET_B pin. The default VOUT_COMMAND value is set by the resistor connected between VSET and AGND and latched when the TPS544x25 devices are powered up from VDD. When the SYNC/RESET_B pin is pulled low, the digital core sets VOUT_COMMAND value back to the default value. The Figure 35 shows the timing diagram for resetting the output voltage. When RESET_B is asserted low, after a short delay (less than 2 µs), the output voltage begins transitioning from its current value to the default value configured by VSET per the slew-rate set in VOUT_TRANSITION_RATE. The VOUT_COMMAND value is not updated to any VOUT_COMMAND programming while SYNC/RESET_B is held low. (A) VOUT_COMMAND adjustment through the PMBus interface ; (B) Reset back to default VOUT_COMMAND value determined by VSET resistor at power up. The slew rate is defined by VOUT_TRANSITION_RATE. Figure 35. Output Voltage Reset 7.3.8 Switching Frequency and Synchronization A resistor from the RT pin to AGND sets the switching frequency. Equation 3 calculates the RRT resistor value. where • RRT is the timing resistor in Ω • fSW is the switching frequency in Hz (3) The TPS544x25 devices are designed to operate between 200 kHz and 1 MHz. The TPS544x25 devices can also synchronize to an external clock which is ±20% of the free-running frequency. The external clock should be applied to the SYNC/RESET_B pin. A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage. If a resistor is connected from VSET pin to AGND to program the initial boot-up voltage, the clock synchronization function is disabled on default, the SYNC/RESET_B pin is configured to RESET function which can reset VOUT when SYNC/RESET_B is logic low. In order to use both VSET and SYNC function, the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) should be set to 1, as shown in Table 4. While the output in regulation and an external clock being applied to SYNC/RESET_B pin, set the FORCE_SYNC bit on the fly causes a sudden change in switching frequency and results in an overshoot or undershoot on the output voltage. |
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