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TPS51513RHBT Datasheet(PDF) 15 Page - Texas Instruments
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TPS51513RHBT Datasheet(HTML) 15 Page - Texas Instruments
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SLUS956A – JUNE 2009 – REVISED FEBRUARY 2010
The TPS51513 incorporates strong, high-performance gate drives with adaptive cross-conduction protection. The
driver uses the state of the DRVL, DRVH, and LL pins to ensure that the top or bottom FET is off before turning
the other on. Fast logic and high-drive currents quickly charge and discharge FET gates to minimize dead-time to
increase efficiency. The top gate driver also includes an internal P-N junction boost diode, decreasing the size
and cost of the external circuitry. For maximum efficiency, this diode can be bypassed externally by connecting a
Schottky diode from V5IN (anode) to VBST (cathode).
The TPS51513 changes the voltage of the internal DAC in a controlled manner to perform SLP entry, SLP exit,
and VID change functions. The slew rate is independent of switching frequency or load. It is set by a resistor
from the ISLEW pin to either GND or VREF (R
sets one rate for SLP exit and VID changes (SR in
the equation below; SR is in units of mV/ms.) A proportional rate is used for soft-start and soft-stop functions. The
ISLEW pin is held at VSLEW
, which is 1.25 V, nominal.
In Equation 4), K
is equal to VSLEW
(1.25V) when R
is tied to GND. To access
the upper range of OCL limit values, connect R
to VREF. In this case, V
is 0.45V (VREF – VSLEW
must be changed accordingly.
The soft-start and soft-stop slew rates are 1/8 of SR. On start-up, the TPS51513 V
output ramps to the level
defined by the VID code (V
). Because of this, the VID code needs to be valid and stable at the time EN is
raised. The calculation for soft-start and soft-stop time is shown in Equation 5.
After approximately 50ms, PG is set LO. Once PG transitions LO, the VID code can change at any time.
Soft Stop Control with Low Impedance Output Termination
The voltage slewing capability is also used to slowly slew the voltage down for a soft-stop without undershoot.
The soft-stop rate equals the soft-start rate. As long as V5IN is available and EN toggles low, the TPS51513
slews from the current VID to approximately 0.3 V. At this point, the DRVL signal is held LO and an internal
transistor of approximately 1-k
Ω is connected from VSNS to GND turns on to keep V
from rising up as a
result of stray leakage currents.
The TPS51513 has a full suite of features to protect the converter power chain as well as the system electronics.
Input Undervoltage Protection (UVLO):
The TPS51513 continuously monitors the voltage on the V5FILT pin to be sure the value is high enough to bias
the device properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts
with approximately 4.4 V and has a nominal 200 mV of hysteresis. This function is not latched. Removing and
restoring the 5-V power supply to the device can be used to reset it. Be sure the voltage at the device discharges
below 1.6 V before rising again to reset the device.. The power input (V
) does not have a UVLO function, so
the circuit operates with power inputs down to approximately 2 × V
Power Good Signals
The TPS51513 has two open-drain power good pins. PGOOD and PG have the following nominal thresholds:
+200mV (also acts as a proportional OVP signal)
Low : V
The differences are:
PG transitions active shortly after V
on power-up; PGOOD has a 6ms nominal delay after
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