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TPS51513RHBT Datasheet(PDF) 14 Page - Texas Instruments

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Part No. TPS51513RHBT
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS51513RHBT Datasheet(HTML) 14 Page - Texas Instruments

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Figure 6 shows the converter operation during transient release. The energy in the inductor is transferred to the
capacitance on the VCORE node above and the output voltage (channel 4) overshoots the desired level (lower
cursor). In this case, the magnitude of the overshoot is 34 mV. Note that the DRVL waveform (channel 2) is high
during the overshoot.
The performance of the same circuit, but with OSR enabled is shown in Figure 7. In this case, the low-side FET
is shut off when overshoot is detected and the energy in the inductor is partially dissipated by the body diodes.
The overshoot is reduced to 18 mV. Also note that the DRVL signal is OFF only long enough to reduce the
Figure 6. Circuit Performance Without Overshoot
Figure 7. Transient Release Performance is Greatly
Improved by the OSR Circuit
OSR is implemented using a comparator between the DROOP and CMP nodes in Figure 1. To implement OSR,
simply terminate the OSRSEL pin to the desired voltage to set the threshold voltage for the comparator. The
settings are:
1. GND = minimum trigger voltage (Maximum overshoot reduction)
2. VREF = medium trigger voltage
3. +3.3V = maximum trigger voltage (Minimum overshoot reduction)
4. 5V = OSR off
Use the highest setting that provides the desired level of overshoot reduction to eliminate the possibility of false
OSR operation.
Light Load Power Saving Features
The TPS51513 has several power saving features to provide excellent efficiency over a very large load range.
The TPS51513 has an automatic pulse skipping skip mode. Regardless of the state of the logic inputs, the
converter senses negative inductor current flow and prevents it by shutting off DRVL. This saves power by
eliminating re-circulating current. Also, when the bottom FET shuts off, the converter enters discontinuous mode,
and the switching frequency decreases, thus reducing switching losses as well.
The SLP signal is used to enter a sleep (SLP) mode. The SLP pin determines the method of entering sleep
mode. If SLP is HI, the converter is allowed to run in skip mode. In this mode, for loads with low leakage current,
the output voltage slew rate is determined by the output capacitance and the leakage current. If SLP is LO, the
device enters PWM mode, and the voltage is actively pulled down by the rate set by RSLEW. The equations are
given below. Because changing VCORE quickly results in large currents charging/discharging the output
capacitors, and this can cause audible noise in inductors and ceramic capacitors, entering a sleep mode with
SLP=HI is recommended.
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Product Folder Link(s) :TPS51513

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