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TPS51513RHBT Datasheet(PDF) 8 Page - Texas Instruments

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Part No. TPS51513RHBT
Description  SINGLE PHASE, D-CAP SYNCHRONOUS BUCK CONTROLLER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TPS51513RHBT Datasheet(HTML) 8 Page - Texas Instruments

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32
3
2
VREF
CSN
CSP
TPS51513
4
5
GSNS
VSNS
DROOP
ISLEW
TONSEL
31
27
29
17
30
21
22
19
18
PGND
V5IN
DRVH
LL
VBST
DRVL
V5FILT
UDG-09086
12
13
14
VID0
VID2
VID1
20
+
DAC
+
VFB
E/A
D/
A
DAC
+
PWM
+
I
AMP
On-Time
Generator
CLK
CO
Smart
Driver
ILIM
23
24
9
25
Control Logic and
Status Circuitry
26
6
8
7
12
1
Analog and
Protection Circuitry
CM
P
VFB
CMP
E
E
P
R
O
M
28
Clamp
TPS51513
SLUS956A – JUNE 2009 – REVISED FEBRUARY 2010
www.ti.com
Table 1. Pin Functions (continued)
PIN #
NAME
I/O
DESCRIPTION
6
REF
I
Termination for test circuitry. Connect to VREF.
9
SLP
I
Sleep mode control. 1-V I/O level. 100-ns de-bounce.
27
TONSEL
I
On-time selection pin. One of four operating frequencies is selected with TONSEL = GND/VREF/3.3V/5V.
Overcurrent protection (OCP) setting. One of eight valley-current limits is selected with the combination of
26
TRIPSEL
I
the ISLEW resistor voltage (GND or VREF) and TRIPSEL = GND/VREF/3.3V/5V.
5-V power input for control circuitry. Has internal 3-
Ω resistor to V5IN. Bypass to GND with a ceramic
30
V5FILT
I
capacitor of 0.1 mF or greater.
21
V5IN
I
5-V driver power input. Bypass to PGND with a ceramic capacitor of 2.2mF or greater.
18
VBST
I
Top N-channel FET bootstrap voltage inputs.
14
VID0
I
15
VID1
I
VID programming bits (MSB to LSB). 1-V I/O level. 100 ns de-bounce.
16
VID2
I
32
VREF
O
1.7-V, 250-mA voltage reference. Bypass to GND with a 0.22-mF capacitor.
Voltage sense line tied directly to VCORE of µP. Tie to VCORE with a 10-Ω resistor to close feedback when
5
VSNS
I
mP is not present.
PAD
Thermal pad; connect to system GND plane with multiple vias.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. TPS51513 Functional Block Diagram
8
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS51513


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