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TPS51513RHBT Datasheet(PDF) 7 Page - Texas Instruments

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Part No. TPS51513RHBT
Description  SINGLE PHASE, D-CAP SYNCHRONOUS BUCK CONTROLLER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TPS51513RHBT Datasheet(HTML) 7 Page - Texas Instruments

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GND
CSP
CSN
GSNS
VSNS
REF
IMON2
IMON
PGOOD
PGND
V5IN
DRVL
LL
VBST
DRVH
PG
PowerPAD
TM
TPS51513
www.ti.com
SLUS956A – JUNE 2009 – REVISED FEBRUARY 2010
TPS51513
(Top View)
Table 1. Pin Functions
PIN #
NAME
I/O
DESCRIPTION
Negative current sense input. Connect to the negative node of current sense resistor or inductor DCR sense
3
CSN
I
RC network.
Positive current sense input. Connect to the positive node of current sense resistor or inductor DCR sense
2
CSP
I
RC network.
Output of gM error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the
31
DROOP
O
transient response. Please see Applications Information section for configurations with no droop.
17
DRVH
O
Top N-channel FET gate drive outputs.
20
DRVL
O
Synchronous N-channel FET gate drive outputs.
25
EN
I
Chip enable signal. 1-V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.
1
GND
Analog / signal ground. Tie to quiet ground plane.
Voltage sense return tied directly to GND of the microprocessor. Tie to GND with a 10-
Ω resistor for
4
GSNS
I
feedback when mP is not present.
Current monitor output. The current out of the IMON output is proportional to the voltage between the CS
8
IMON
O
inputs.
7
IMON2
O
Connection point for IMON mirror matching resistor.
Clamp reference input for the IMON signal; 3.6-V maximum. Bypass to GND with a ceramic capacitor of 0.1
12
IMONC
I
mF or greater.
Precision current set-point for slew rate control. Tie the ISLEW resistor to GND to select the low range of
29
ISLEW
I
OCP values; VREF for the higher range.
19
LL
I/O
Top N-channel FET gate drive return. Also, input for adaptive gate drive timing.
10
11
NC
No connection; leave floating.
13
Overshoot reduction (OSR) setting. One of three OSR settings is selected with OSRSEL = GND/VREF/3.3
28
OSRSEL
I
V. OSRSEL = 5 V disables OSR.
Negative active power good output. Transitions low of approximately 50 ms after VCORE reaches the
24
PG
O
VID-defined level. Open-drain. Leave open if unused.
22
PGND
Power return for the synchronous N-channel FET gate driver outputs.
23
PGOOD
O
Power Good output. 6-ms nominal delay from PG. Open-drain.
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s) :TPS51513


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