TPS53624_16 datasheet(7/44 Pages) TI1

Part #	TPS53624

Description	Dual Phase, D-CAP, Eco-mode Step-Down Controller with 8-Bit DAC

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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MODE

GND

CSP2

CSN2

CSN1

CSP1

GFB

VFB

THRM

THAL

TPS53624

DRVH2

VBST2

LL2

DRVL2

V5IN

PGND

DRVL1

LL1

VBST1

DRVH1

TPS53624

www.ti.com

SLUSB66 – MARCH 2013

DEVICE INFORMATION

RHA PACKAGE

40 PINS

(TOP VIEW)

Table 1. PIN FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

CSP1

6

I

Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR

sense R-C network.

CSP2

3

I

CSN1

5

I

Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR

sense RC network.

CSN2

4

I

Output of gM error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the

DROOP

39

O

transient response.

DRVH1

21

O

High-side N-channel MOSFET gate drive outputs.

DRVH2

30

O

DRVL1

24

O

Synchronous N-channel MOSFET gate drive outputs.

DRVL2

27

O

Controller enable. 3.3-V I/O level; 100-ns de-bounce. Logic high 3.3-V enables the controller. Logic low stops

EN

35

I

the controller.

GND

2

—

Return for analog circuits.

Voltage sense return tied directly to GND of the microprocessor. Tie to GND with a 100-

Ω resistor to close

GFB

7

I

feedback when the microprocessor is not in the socket.

Current monitor output. VIMON = ΣVISENSE × K × RIMON. Reference RIMON to GNDSNS. Voltage is clamped at

IMON

11

O

1.1-V maximum.

LL1

23

I/O

High-side N-channel MOSFET gate drive return. Also, input for adaptive gate drive timing.

LL2

28

I/O

MODE

1

—

Tie to GND to select CPU mode.

OSRSEL

32

O

Overshoot reduction (OSR) setting. The OSR threshold can be selected or OSR can be disabled.

Negative active power good output; Open drain. Transitions low of approximately 50 ms after VOUT reaches

PG

34

O

the VID level. Leave open if unused.

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