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VSC7959 Datasheet(PDF) 7 Page - Vitesse Semiconductor Corporation |
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VSC7959 Datasheet(HTML) 7 Page - Vitesse Semiconductor Corporation |
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7 / 10 page  VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7959 3.125Gb/s CML Limiting Amplifier with LOS Detect G52358-0, Rev 2.0 Page 7 02/09/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Detailed Description The VSC7959 is a high speed limiting amplifier with Loss-of-Signal (LOS) detect. The device is designed to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The VSC7959 has current-mode logic (CML) outputs. The VSC7961 provides the same functionality as the VSC7959 with positive emitter-coupled logic (PECL) outputs. The key features of the VSC7959 are Loss-of- Signal (LOS) detect, output offset correction, output squelch, adjustable output levels, low power supply cur- rent, and fast rise and fall times. The inputs of the device provide 100 Ω input impedance between IN+ and IN- and are intended to be DC- coupled. The CML output circuits are designed to tolerate output impedance mismatches and may be AC- or DC-coupled. Loss of Signal (LOS) Detect This features utilizes an RMS power detector with programmable LOS indicator to provide two outputs, LOS and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and LOS, change state. See the Loss of Signal Specifications (Table 3) for setting the resistor value between TH and ground. The Loss of Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact. Optional Squelch Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not asserted, the outputs will not be squelched. Offset Correction This feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not cause the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low- frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low frequency cut-off is 2MHz. If a 0.1 µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1 µF capacitor between CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low fre- quency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation: fOC = 43 / [2π * 35k (CZ + 100pF)] = 196 • 10-6 / (CZ + 100pF) = 196 • 10-6 / (0.1 µF + 100pF) = 1.96kHz |
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