TPS40140RHHTG4 datasheet(50/68 Pages) TI1 | Dual or 2-Phase, Stackable Controller

Part No.	TPS40140RHHTG4

Description	Dual or 2-Phase, Stackable Controller

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OUT

RIPPLE

RIP _ NORM

SW

V

(1 D)

I

L f

´

-

=

´

PH

RIP _ NORN

m

m 1

N

(D

) (

D)

N

I

D (1 D)

+

´

-

´

-

=

´

-

TPS40140

SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

www.ti.com

9.2.2.1 Design Requirements

Table 7. Design Goal Parameters

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VIN

Input voltage

10.8

12

13.2

V

VIN(ripple)

Input ripple voltage

IOUT = 32 A

0.15

V

VOUT

Output voltage

1.5

V

Line regulation

10.8 V

≤ VIN ≤ 13.2 V

0.5%

Load regulation

0 V

≤ IOUT ≤ 32 A

0.5%

VP-P

Output ripple voltage

IOUT = 32 A

30

mV

ΔVOUT

Output voltage deviation during load

ΔIOUT = 15 A, VIN = 12 V

50

mV

transient

IOUT

Output current

10.8 V

≤ VIN ≤ 13.2 V

0

32

A

η

Efficiency

IOUT = 32 A VIN = 12 V

87%

fSW

Switching frequency

500

kHz

9.2.2.2 Detailed Design Procedure

9.2.2.2.1

Step 1: Output Capacitor Selection

The output capacitor is typically selected by the output load transient response requirement. Equation 23 in the

dual output design example is used. The inductor L in the equation is equal to the phase inductance divided by

number of phases.

Based on a 15-A load transient with a maximum of 50 mV deviation, a minimum 795-

μF output capacitor is

required. In the design, four 330-

μF, 2 V, SP capacitor are selected to meet this requirement. Each capacitor has

an ESR of 6 m

Ω.

Another criterion for capacitor selection is the output ripple voltage that is determined mainly by the capacitance

and the ESR.

Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a single

phase. The ripple cancellation factor is expressed in Equation 56.

where

•

D is the duty cycle for a single phase

•

NPH is the number of active phases, here it is equal to 2

•

m = floor (NPH × D) is the maximum integer that does not exceed the (NPH × D), here m is 0

(56)

The output ripple current is then calculated in Equation 57. The maximum output ripple current is 4.3 A with

maximum input voltage.

(57)

With 1.32 mF output capacitance, the ripple voltage at the capacitor is calculated to be 0.82 mV. In the

specification, the output ripple voltage should be less than 30 mV, so based on Equation 24, the required

maximum ESR is 6.7 m

Ω. The selected capacitors can meet this requirement.

9.2.2.2.2

Step 2: Input Capacitor Selection

The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the

maximum ESR can be estimated by Equation 25 and Equation 26 in the dual output design example. The phase

current should be used in the calculation.

For this design, VRIPPLE(CIN) assume is 100mV and VRIPPLE(CinESR) is 50 mV, so the calculated minimum

capacitance is 40

μF and the maximum ESR is 2.7 mΩ. Choosing four 22-μF, 16-V, 2-mΩ ESR ceramic

capacitors meet this requirement.

50

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