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TPS40140RHHT Datasheet(PDF) 13 Page - Texas Instruments

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Part # TPS40140RHHT
Description  Dual or 2-Phase, Stackable Controller
Download  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40140RHHT Datasheet(HTML) 13 Page - Texas Instruments

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17
8
31
32
27
26
25
24
VDD
BP5
CS1
CSRT1
BOOT1
HDRV1
SW1
LDRV1
TPS40140
34
2
3
1
ILIM1
VOUT
GSNS
DIFFO
36
33
35
9
FB1
TRK1
COMP1
FB2
12
10
14
13
TRK2
COMP2
CS2
CSRT2
11
29
16
5
ILIM2
UVLO_CE1
UVLO_CE2
RT
4
PHSEL
U1
V5REG
U3
ICTLR1
+
U2
OC1
+
U9
0.7 V
VREF
+
+
U10
U13
6 mA
to
12 mA
0.7 V
VREF
+
+
U14
U20
U11
–
+
U15
U22
ICTLR2
+
U21
6 mA
to
12 mA
OC2
U27
PGOOD
Control
U23
UV/OV/OC
Control
FB1
FB2
OC1
OC2
U4
RAMP1
+
U25
CLOCK
TRK1
TRK2
FB1
FB2
U16
RAMP2
U26
RAMP GEN
MCLK
PWM1
U6
PWM
Logic
PWM2
U5
+
–
+
U17
U7
Anti
Cross
Conduction
U18
Anti
Cross
Conduction
U8
21 VREG
18
19
20
BOOT2
HDRV2
SW2
U19
23 PGND
VREG
U12
22 LDRV2
VREG
U24
30
15
6
PGOOD1
PGOOD2
VSHARE
7
GND
CLKIO
28
RAMP1
RAMP2
1.8 V
UDG-08198
TPS40140
www.ti.com
SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Clock Master and Clock Slave
A controller may function as a 'clock master' or a 'clock slave'. The term 'clock master' designates the controller,
in a multi-controller configuration, that generates the CLKIO signal for clock synchronization between the clock
master and the clock slaves. The CLKIO signal is generated when the 'RT' pin of the clock master is terminated
with a resistor to ground and the PHSEL pin of the clock master is terminated with a resistor, or resistor string, to
ground. The 'Clock slave' is configured by connecting the RT pin to BP5. Then the Clock slave receives the
CLKIO signal from the clock master. The phasing of the slave is accomplished with a resistor string tied to the
PHSEL pin. More information is covered in the Clock Master, PHSEL, and CLKIO Configurations section.
Copyright © 2005–2015, Texas Instruments Incorporated
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