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TPS40140RHHT Datasheet(PDF) 40 Page - Texas Instruments |
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TPS40140RHHT Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 68 page  + + + + + + + + R7 10K C11 2.2 n R5 50 R9 50 VOUT1 BODE12 BODE11 R13 510k R23 39K VSHR R15 22.6K R14 62K R16 33K C20 1uF R18 698k R19 50 R20 50 C21 1uF C23 2.2n BP5 BODE21 BODE21 R22 10K R26 2.7k R24 open C27 open C26 470pF R29 10K PG2 C37 0.022uF TRK2 AGND1 C36 1uF R8 8.66K C7 330pF C30 0.1uF R28 10k R31 10K AGND2 C29 0.1uF R21 4.7 U1 TPS40140RHH C22 0.1uF R17 4.7 D2 BAT54HT1 C24 0.1uF C25 4.7uF R27 10K C13 0.1uF C12 0.1uF R12 4.7 D1 BAT54HT1 R6 10K R32 10K R33 10K C6 1uF C5 0.022uF TRK1 R2 10k C8 0.1uF R3 open C9 open 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 DIFFO VOUT GSNS PHSEL RT VSHARE GND BP5 FB2 BOOT1 HDRV1 SW1 LDRV1 PGND LDRV2 VREG SW2 HDRV2 Q6 RJK0301DPB Q8 RJK0305DPB Q5 RJK0301DPB Q7 Open R30 10K L2 1.5uH R25 1 C28 3.3n SW2 C31 220u C32 220u C33 220u C34 220u C35 22uF GNDTP3 C41 22uF C40 22uF C39 22uF C38 22uF VOUT2 3.3V @ 20A J10 4 3 2 1 J9 1.5V @ 20A 1 2 3 4 C14 220u C15 220u C16 220u C17 220u C18 22uF R10 51.1 R11 51.1 VOUT1 J2 1 2 Remote Sense+ Remote Sense- Q2 Open Q4 RJK0301DPB Q3 RJK0301DPB Q1 RJK0305DPB R4 1 C10 3.3n SW1 12Vin +/- 10% GND J1 1 2 3 4 GNDTP1 C1 22uF C2 22uF C3 22uF C4 22uF R1 10K L1 1uH VOUT2 ILIM2 VSHR PHSELIN GSNS RT COMP1 TRK1 CS1 CSRT1 BP5 1 1 12VIN UVLO1 UVLO1 CLKIO VREG 1 1 1 1 1 1 1 VREG BP5 COMP2 VOUT2 TRK2 PGOOD2 BP5 UVLO2 12VIN VREG BP5 1 2 3 1 2 3 1 2 3 1 2 3 4 4 4 5 5 4 5 5 12VIN CS2 VOUT2 GSNS VOUT1 CSRT1 CS1 12VIN 3 2 1 4 4 4 4 5 5 5 5 3 2 1 3 2 1 3 2 1 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.2 Typical Application 9.2.1 Application 1: Dual-Output Configuration from 12 to 3.3 V and 1.5 V DC-DC Converter Using a TPS40140 Figure 40 shows the schematic of the dual output converter design. Figure 40. Dual-Output Converter Schematic 9.2.1.1 Design Requirements The following example shows the design process and component selection for a dual output synchronous buck converter using TPS40140. Table 6 provides the design goal parameters. Only the calculated numbers for the 1.5-V output are shown, however, the equations are suitable for both channel design. A list of symbol definitions is found at the end of this section. Table 6. Design Goal Parameters PARAMETER TEST CONDITION MIN TYP MAX UNIT VIN Input voltage 10.8 12 13.2 V VIN(ripple) Input ripple voltage IOUT = 20 A 0.15 V VOUT Output voltage 1.5 V Line regulation 10.8 V ≤ VIN ≤ 13.2 V 0.5% Load regulation 0 V ≤ IOUT ≤ 20 A 0.5% VP-P Output ripple voltage IOUT = 20 A 30 mV ΔVOUT Output voltage deviation during load ΔIOUT = 10 A, VIN = 12 V 80 mV transient IOUT Output current 10.8 V ≤ VIN ≤ 13.2 V 0 20 A η Efficiency IOUT = 20 A VIN = 12 V 87% fSW Switching frequency 500 kHz 40 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 |
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