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TPS40140RHHT Datasheet(PDF) 29 Page - Texas Instruments

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Part No. TPS40140RHHT
Description  Dual or 2-Phase, Stackable Controller
Download  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40140RHHT Datasheet(HTML) 29 Page - Texas Instruments

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M_CH1
M_CH2
S_CH1
S_CH2−
NOT USED IN3PH
M
R
S
TPS40140
www.ti.com
SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015
9.1.4.1 Basic Configurations for 2, 4, 6, 8, 12, or 16 Phases
The solid square boxes in Figure 26 represent the PHSEL pin of the master (M) controller or a numbered slave
controller (S1-S7). The labels on the spokes of the wheels indicate a master Channel 1 and master Channel 2
(M_CH1 and M_CH2) and numbered slaves Channel 1 and slave Channel 2 (Sn_CH1 and Sn_CH2). The
Channel 1 and Channel 2 of a given master or slave is always 180° out-of-phase.
The master and slaves are automatically configured for proper phasing based on the resistor string from the
master to the slaves. All the resistors are 39 k
Ω to 41.2 kΩ. Part (A) above shows a single controller operating
two phases 180° out-of-phase. Part (B) above shows four phase operation. This is configured by connecting a
single resistor from the master PHSEL to GND and grounding the slave PHSEL pin. The individual channels are
90° out-of-phase. Part (C) above shows six phase operation. This is configured by connecting two resistors from
the master PHSEL to GND. The first resistor tap is connected to slave2 PHSEL pin and then grounding the
slave1 PHSEL pin. The individual channels are 60°out-of-phase. Part (D) above shows eight phase operation.
This is configured by connecting three resistors from the master PHSEL to GND. The first resistor tap is
connected to slave3 PHSEL pin. The second resistor tap is connected to slave2 PHSEL pin and then grounding
the slave1 PHSEL pin. The individual channels are 45° out-of-phase. Part (F) above shows twelve phase
operation. This is configured by connecting two resistors from the master PHSEL to GND. The master PHSEL
pin is also connected to slave5 PHSEL pin. The first resistor tap is connected to slave2 and slave4 PHSEL pins
and then grounding the slave1 and slave3 PHSEL pins. The individual channels are 30° out-of-phase.
Additionally, the ILIM2 pins of slave5, slave4 and slave3 are left open (internal pullup) or externally connected to
BP5. Part (G) above shows sixteen phase operation. This is configured by connecting three resistors from the
master PHSEL to GND. The master PHSEL pin is also connected to slave7 PHSEL pin. The first resistor tap is
connected to slave3 and slave6 PHSEL pins. The second resistor tap is connected to slave2 and slave5 PHSEL
pins and then grounding the slave1 and slave4 PHSEL pins. The individual channels are 22.5° out-of-phase.
Additionally, the ILIM2 pins of slave7, slave6, slave5, and slave4 are left open (internal pullup) or externally
connected to BP5.
9.1.4.2 Configuring for Other Number of Phases
Configuring for other than 2, 4, 6, 8, 12 or 16 phases is simply a matter of not attaching one or more slave
controllers. The phasing between master and populated slaves is as shown above. For example a 3-phase
system could be configured with a master CH1 and master CH2 and 1 phase of a slave. Referring to Part (B)
above, the 3 phases could be master CH1, master CH2 and slave CH1 or slave CH2 as shown in Figure 27.
Figure 27. Phase System: 2 Channels of the Master and 1 Channel of the Slave
The 3-phase system could also be configured with 1 channel of the master and 2 channels of the slave.
Referring to Part (B) above, the 3 phases could be master CH1 or master CH2 and slave CH1 and slave CH2. In
either of these configurations there is 90° between two of the channels and 180° between the other channel. The
unused channel could be another independent output voltage whose clocking would occupy the phase not used
in the 3-phase system. This philosophy can be used for any number of phases not shown in Figure 26, Clock
Phasing Summary.
For example, a 10-phase system could be configured as shown in Figure 28.
Copyright © 2005–2015, Texas Instruments Incorporated
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