TPS40140RHHRG4 datasheet(7/68 Pages) TI1 | Dual or 2-Phase, Stackable Controller

Part No.	TPS40140RHHRG4

Description	Dual or 2-Phase, Stackable Controller

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Manufacturer	TI1 [Texas Instruments]

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TPS40140

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SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

Electrical Characteristics (continued)

–40°C

≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5,

ƒSW = 300 kHz, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER CH1, ERROR AMPLIFIER CH2

Input common mode range(1)

0

0.7

2.0

V

Input bias current(1)

VFB = 0.7 V

10

nA

FBx voltage(1)

0.6965

0.700

0.7035

V

Output source current

VCOMP = 1.1 V, VFB = 0.6 V

1

2

mA

Output sink current

VCOMP = 1.1 V, VFB = BP5

1

2

mA

BW(1)

8

12

MHz

Open loop gain(1)

60

90

dB

VOLTAGE TRACKING (TRK1, TRK2)

After EN, before PWM and during hiccup mode

5

6.0

7.3

SS source current

µA

After first PWM pulse

10

12.5

15

Fault enable threshold(1)

1.4

V

Internal clamp voltage(1)

2.4

V

SS sink resistance(1)

Pulldown resistance

1

k

Ω

CURRENT SENSE AMPLIFIERS (CS1, CS2)

Differential input voltage

–60

60

mV

Input offset voltage

CS1, CS2, trimmed

–2.0

0

2.0

mV

Ac

Gain transfer to PWM COMP

5 mV < VCS < 60 mV, VCSRT = 1.5 V

12

13

14

V/V

Input common mode(1)

0

5.8

V

CSA

Input bias current

100

nA

DIFFERENTIAL AMPLIFIER (DIFFO)

Gain

1.0 V < VOUT < 5.8 V

0.997

1

1.003

V/V

Input common mode range(1)

0

5.8

V

VOUT – VVGSNS = 2 V, VDIFFO > 1.98 V,

Output source current(1)

2

VDD-VOUT > 2 V

VOUT – VVGSNS = 2 V, VDIFFO > 2.02 V VDD –

Output source current(1)

1

mA

VOUT = 1 V

VOUT – VVGSNS = 2 V,

Output sink current(1)

2

VDIFFO > 2.02 V

Unity gain bandwidth(1)

5

8

MHz

Input Impedance, non inverting(1)

VOUT to GND

60

k

Ω

Input Impedance, inverting(1)

GSNS to DIFFO

60

GATE DRIVERS

HDRV1, HDRV2 source on-

VBOOT1, VBOOT2 = 5 V, VSW1 = VSW2 = 0 V,

1

2

3

resistance

Sourcing 100 mA

HDRV1, HDRV2 sink on-

VVREG = 5 V, VSW1 = VSW2 = 0 V,

0.5

1.2

2

resistance

Sinking 100 mA

Ω

LDRV1, LDRV2 source on-

VVREG = 5 V, VSW1 = VSW2 = 0 V,

1

2

3

resistance

Sourcing 100 mA

LDRV1, LDRV2 sink on-

VVREG = 5 V, VSW1 = VSW2 = 0 V,

0.3

0.65

1

resistance

Sinking 100 mA

tRISE

HDRVx rise time(1)

CLOAD= 3.3 nF

25

75

tFALL

HDRVx fall time(1)

CLOAD= 3.3 nF

25

75

tRISE

LDRVx rise time(1)

CLOAD= 3.3 nF

25

75

ns

tFALL

LDRVx fall time(1)

CLOAD= 3.3 nF

20

60

Minimum controllable on-time

CLOAD= 3.3 nF

50

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