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TPS40140RHHRG4 Datasheet(PDF) 57 Page - Texas Instruments |
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TPS40140RHHRG4 Datasheet(HTML) 57 Page - Texas Instruments |
57 / 68 page ![]() L NPH 1 2 3 4 J1 C1 47 mF VIN VINTP1 GNDTP3 Master CLKIO VIN PHSELIN COMP1 VSHR GND VOUT Slave CLKIO VIN GND COMP1 VSHR GND VOUT 10 kW VOUT C2 180 mF VOUTTP1 V OUT GND GNDTP5 PHSELIN NC S1 R3 39 kW GND UDG-08085 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Figure 65. Motherboard Schematic The design goal parameters are given in Table 8. Table 8. Design Goal Parameters PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input Voltage 10.8 12 13.2 V VOUT Output voltage 1.8 V VRIPPLE Output ripple IO = 20 A 20 mV IPH Phase current 5 A fsw Switching frequency 650 kHz NPH Phase number 4 9.3.1.1 Step 1: Output Capacitor Selection The output capacitor is typically selected by the output load transient response requirement. Equation 23 in the dual output design example is used. Also, as mentioned in the two phase design example, the inductor is equivalent to . Based on a 10-A load transient with a maximum of 30 mV deviation, a minimum 370- μF output capacitor is required. In the design, one 180 μF, 6.3 V, SP capacitor is placed on the mother board. Four 22- μF, 6,3-V ceramic capacitors are placed on each module. The total output capacitance is 356 μF. The output ripple current cancellation factor is calculated to be 0.526 with maximum input voltage based on Equation 56. So the maximum output ripple current is calculated by: Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 57 Product Folder Links: TPS40140 |
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