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TPS40140RHHRG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS40140RHHRG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 68 page ![]() TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN(1) I/O DESCRIPTION NAME NO. COMP2 10 O Output of the error amplifier, CH2. The voltage at this pin determines the duty cycle for the PWM2. These pins are used to sense the CH1 phase current. Inductor current can be sensed with an external current CS1 31 I sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for these signals must be connected directly at the current sense element. These pins are used to sense the CH2 phase current. Inductor current can be sensed with an external current CS2 14 I sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for these signals must be connected directly at the current sense element. Output of the differential amplifier. The output voltage of the differential amplifier is limited to 5.8 V. For remote sensing, the voltage at this pin represents the true output voltage without I × R drops that result from high DIFFO 1 O current in the PCB traces. The VOUT and GSNS pins must be connected directly at the point of load where regulation is required. See Layout Guidelines for more information. Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the current CSRT1 32 I sense element. Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the current CSRT2 13 I sense element. Inverting input of the error amplifier for CH1. In closed loop operation, the voltage at this pin is nominally 700 FB1 36 I mV. This pin is also monitored for PGOOD1 and undervoltage on CH1. Inverting input of the error amplifier for CH2. In closed loop operation, the voltage at this pin is nominally 700 FB2 9 I mV. This pin is also monitored for PGOOD2 and undervoltage on CH2. GND 7 — Low noise ground connection to the device. Inverting input of the differential amplifier. This pin should be connected to ground at the load. If the differential GSNS 3 I amplifier is not used, tie this pin to GND or leave open. Gate drive output for the high-side N-channel MOSFET switch for CH1. Output is referenced to SW1 and is HDRV1 26 O bootstrapped for enhancement of the high side switch. Gate drive output for the high-side N-channel MOSFET switch for CH2. Output is referenced to SW2 and is HRDV2 19 O bootstrapped for enhancement of the high side switch. Used to set the cycle-by-cycle current limit threshold for CH1. If the ILIM1 threshold is reached, the PWM pulse ILIM1 34 I is terminated and the converter delivers limited current to the output. Used to set the cycle-by-cycle current limit threshold for CH2. If the ILIM2 threshold is reached, the PWM pulse ILIM2 11 I is terminated and the converter delivers limited current to the output. LRDV1 24 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1. LRDV2 22 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2. Power good indicators for CH1 output voltage. This open-drain output connects to a voltage via an external PGOOD1 30 O resistor Power good indicators for CH2 output voltage. This open-drain output connects to a voltage via an external PGOOD2 15 O resistor Power ground reference for the controller lower gate drivers. There should be a high current return path from PGND 23 — the sources of the lower MOSFETs to this pin. A 20 μA current flows from this pin. In a single controller design, this pin should be grounded. In a multi PHSEL 4 O controller configuration, a 39- k Ω resistor string sets the voltage on this pin determines the proper phasing for the slaves. See the section on Clock Master, PHSEL, and CLKIO Configurations. RT 5 I Connecting a resistor from this pin to ground sets the oscillator frequency. Connect to the switched node on converter CH1. It is the return for the CH 1 upper gate driver. There should SW1 25 I be a high current return path from the source of the upper MOSFET to this pin. This pin is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. Connect to the switched node on converter CH2. It is the return for the CH 2 upper gate driver. There should SW2 20 I be a high current return path from the source of the upper MOSFET to this pin. This pin is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. This is an input to the non-inverting input of the error amplifier CH1. This pin is normally connected to the soft- TRK1 33 I start capacitor or to another voltage that is tracked. This is an input to the non-inverting input of the error amplifier CH2. This pin is normally connected to the soft- TRK2 12 I start capacitor or to another voltage that is tracked. A voltage divider from VIN to this pin determines the input voltage that CH1 starts. When the voltage is UVLO_CE1 29 I between 0.5 and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH1 soft start is allowed to begin. 4 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 |
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