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TPS40140 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. TPS40140
Description  Dual or 2-Phase, Stackable Controller
Download  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40140 Datasheet(HTML) 6 Page - Texas Instruments

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TPS40140
SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015
www.ti.com
7.4 Thermal Information
TPS40140
RHH
THERMAL METRIC(1)
UNIT
(VQFN)
36 PINS
RθJA
Junction-to-ambient thermal resistance
30.8
RθJC(top)
Junction-to-case (top) thermal resistance
18.4
RθJB
Junction-to-board thermal resistance
5.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.7
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
–40°C
≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5,
ƒSW = 300 kHz, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD INPUT SUPPLY
Operating voltage range
4.5
12
15
V
Shutdown current
UVLO_CE1 = UVLO_CE2 = GND
1
10
µA
BP5 INPUT SUPPLY
Operating voltage range
4.5
5.0
5.5
V
BP5 operating current
2
3
5
mA
Rising BP5 turnon
4.0
4.25
4.45
V
BP5 turnoff hysteresis
100
220
400
mV
Standby mode current(1)
UVLO_CEx = 1.7 V
2.8
mA
VREG
7 V < VDD < 15 V
4.5
5.1
5.5
V
Output current
0
100
mA
OSCILLATOR, RT
Phase frequency accuracy
RRT= 110 kΩ
300
kHz
Phase frequency set range
150
1000
kHz
RT(1)
25 k
Ω ≤ RRT ≤ 500 kΩ
0.7
V
UNDERVOLTAGE LOCKOUT (UVLO_CE1, UVLO_CE2)
Enable threshold, standby mode
Internal 5VREG regulator enabled
0.5
1.0
1.5
V
UVLO threshold
PWM Switching enabled
1.9
2
2.1
V
UVLO hysteresis
At the UVLO_CEx pin
40
mV
UVLO_CE1, UVLO_CE2 bias
1
μA
current(1)
PWM
2-phase, 4-phase, 8-phase, or 16-phase
87.5%
Maximum duty cycle per
DMAX
channel(1)
3-phase, 6-phase, or 12-phase
83.3%
tON(min)
Minimum controllable pulse width
70
ns
PWM COMPARATOR
Input offset voltage
–3
3
mV
VSHARE
IVSHR = 0
1.785
1.8
1.815
V
See(1)
–30
μA < iVSHR < 50 μA
1.785
1.8
1.815
V
(1)
Specified by design. Not production tested.
6
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Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: TPS40140


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