TPS40140 datasheet(17/68 Pages) TI1 | Dual or 2-Phase, Stackable Controller

Part No.	TPS40140

Description	Dual or 2-Phase, Stackable Controller

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Manufacturer	TI1 [Texas Instruments]

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17 / 68 page

R

SET + VOUT

1

V

IN2

*

1

V

IN1

100 kW

TPS40140

www.ti.com

SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

Application Information (continued)

If the controller has free running operation (in clock master mode) before receiving the external clock, the

switching frequency is set by connecting a resistor from the RT pin to GND. In order to receive the external

clock, the PHSEL pin should be connected to GND to disable the output of CLKIO pin. A 500-

Ω resistor is

recommended to be placed between the external clock and the CLKIO pin. When dynamically shorting the RT

pin to BP5 through a switch, the controller switches to clock slave mode and starts to synchronize to the external

clock.

9.1.2 Split Input Voltage Operation

It may be advantageous to operate a master controller’s power stages from VIN 1, different from the slave

controller(s) power stages, VIN 2 where VIN1 > VIN 2. This enables the system designer to optimize the current

taken from the system input voltages. In order to balance the output currents, a programmed offset is applied to

ILIM2 of the slave controller(s). The voltage on this pin sets the offset current for channel 2.

The ramp offset is determined by a resistor, RSET, connected to the ILIM2 pin of the slave, and is given by:

(1)

9.1.3 Configuring Single and Multiple ICs

The controller may be configured for a single output, 2-phase mode or a dual output voltage mode. In the dual

output mode the input voltages and the output voltages are independent of each other. In 2-phase mode the

input voltages and output voltages are tied together, respectively and certain other pins must be configured. The

two phases of a single controller are always 180° out-of-phase. The entry in Table 3 that refer to "TO

NETWORK" means the normal resistor-capacitor network used for control loop compensation. The other entries

refer to components that are typically connected to the device pin.

Table 2. Configuring Clock Mode

TIMING RESISTANCE VOLTAGE (V)

CLOCK MODE

< 0.7 V (resistor to GND)

Master (or single device)

> 1 V (tied to VREG or VDD)

Slave

9.1.3.1 Single Device Operation

A single controller may be configured as a 2-phase or dual output. A summary of the modes and device pin

connections for a single controller is given in Table 3. The basic schematic of a single controller operating in a 2-

phase mode is shown in Figure 17. The dual output schematic is shown in Figure 18.

Table 3. TPS40140 Single Device Mode Selection and Pin Configuration

DEVICE PIN

FOR 2 PHASE MODE

FOR DUAL OUTPUT MODE

COMP1

TO NETWORK

COMP2

COMP1

TO NETWORK

TRK1

TO SS CAPACITOR

TRK2

TO BP5

TO SS CAPACITOR

ILIM1

TO SET RESISTORS

ILIM2

GND

TO SET RESISTORS

FB1

TO NETWORK

FB2

GND

TO NETWORK

PHSEL

GND

PGOOD1

TO PULLUP RESISTOR

TO PULL-UP RESISTOR

PGOOD1

TO PULLUP RESISTOR

TO PULL-UP RESISTOR

CLKIO

OPEN

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