TPS40140_16 datasheet(14/68 Pages) TI1 | Dual or 2-Phase, Stackable Controller

Part No.	TPS40140

Description	Dual or 2-Phase, Stackable Controller

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Manufacturer	TI1 [Texas Instruments]

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14 / 68 page

TPS40140

SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

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Feature Description (continued)

8.3.2 Voltage Master and Voltage Slave

A voltage master has the channel that monitors the output voltage and generates the 'COMP' signal for voltage

regulation. A Voltage slave channel is configured by connecting the TRKx pin to BP5. Then the COMP signal

from the master is connected to the COMPx pin on the Voltage slave. When the TRKx pin is connected to BP5

the COMPx output for that channel is put in a high impedance state, allowing the regulation for that channel to be

controlled by the voltage master COMP signal.

8.3.3 Power Good

The PGOOD1, PGOOD2 pins indicate when the inputs and output are within their specified ranges of operation.

Also monitored are the UVLO_CE1, UVLO_CE2 and TRK1 and TRK2 pins. The PGOOD has a high impedance

when indicating inputs and outputs are within specified limits and is pulled low to indicate an out of limits

condition. The PGOOD signal is held low until the respective TRK1 or TRK2 pin voltages exceed 1.4 V, then the

undervoltage, overcurrent or overtemperature controls the state of PGOOD.

8.3.4 Power-On Reset (POR)

The internal POR function ensures the VREG and BP5 voltages are within their regulation windows before the

controller is allowed to start.

8.3.5 Overcurrent

The operation during an overcurrent condition is described in the ‘Overcurrent Detection and Hiccup Mode’

section. In summary, when the controller detects 7 clock cycles of an overcurrent condition, the upper and lower

MOSFETs are turned off and the controller enters a 'hiccup' mode'. After seven soft start cycles, normal

switching is attempted. If the overcurrent has cleared, normal operation resumes, otherwise the sequence

repeats.

8.3.6 Output Undervoltage Protection

If the output voltage, as sensed by U23 of the functional block diagram on the FB pin becomes less than 0.588

V, the undervoltage protection threshold (84% of VREF), the controller enters the hiccup mode as described in the

Overcurrent Detection and Hiccup Mode section.

8.3.7 Output Overvoltage Protection

The TPS40140 includes an output overvoltage protection mechanism. This mechanism is designed to turn on the

low-side FET when the FB pin voltages exceeds the overvoltage protection threshold of 810-mV (typical). The

high-side FET turns off and the low-side FET turns on and stays on until the voltage on the FB drops below the

undervoltage threshold. The controller then enters a hiccup recovery cycle as in the undervoltage case. The

output overvoltage protection scheme is active at all times. If at any time when the controller is enabled, the FB

pin voltage exceeds the overvoltage threshold, the low-side FET turns on until the FB pin voltage falls below the

undervoltage threshold.

Output overvoltage is defined as any voltage greater than the regulation level that appears on the output.

Overvoltage protection is accomplished by the feedback loop monitoring the output voltage via the FB pin. If,

during operation the output voltage experiences an overvoltage condition the FB pin voltage rises and the control

loop turns the upper FET off and the lower FET is turned on until the output returns to set level. This puts the

overvoltage channel in a boost mode configuration and tends to cause the input voltage to be boosted up.

If the output overvoltage condition exists prior to the controller PWM switching starting, that is, no switching has

commenced, the overvoltaged channel does not start PWM switching. This controller allows for operating with a

prebiased output. Because the output is greater than the regulation voltage, no PWM switching occurs.

DESIGN HINT

Ensure there is sufficient load on the input voltage to prevent excessive boosting.

14

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