TPS40140_16 datasheet(16/68 Pages) TI1 | Dual or 2-Phase, Stackable Controller

Part No.	TPS40140

Description	Dual or 2-Phase, Stackable Controller

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PWM −A

1

2

3

4

5

6

7

8

9

EXT CLK−A

EXT CLK−S

1

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3

4

5

6

7

8

1

11

10

3

2

PWM −S

UDG−06032

TPS40140

SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

www.ti.com

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The following sections are partitioned to facilitate applying the TPS40140 in various modes and configurations.

The first sections describe functions that are used in all configurations. The following sections are specific to the

configuration (that is, single controller, multiple controllers, master and slave).

9.1.1 Synchronizing a Single Controller to an External Clock

The TPS40140 has the ability to synchronize a single controller to an external clock. The clock must be a pulse

stream at 6 or 8 times the master PWM frequency. See Figure 16.

Figure 16. Synchronizing a Single Controller to an External Clock

Synchronizing the single controller to an external clock is similar to synchronizing a clock slave to a clock master.

The single controller is put in clock slave mode by connecting the RT pin to BP5, disabling the internal clock

generator. If the external CLKIO signal is a clock stream without any missing pulses, the master synchronize to

an arbitrary pulse so there is no determinant phase synchronization. Without a missing pulse, the PWM

frequency is 1/8 of the external clock. If the external CLKIO signal has a missing pulse every 6 cycles or 8

cycles, the controller synchronizes based on the missing pulse which would be in the 6th or 8th position. With the

missing pulse, the phase synchronization of the master, to the missing pulse, can be controlled by the voltage on

the PHSEL pin. See the section on DIGITAL CLOCK SYNCHRONIZATION. Phase shifting would also be

desirable if more than one controller were to be synchronized to the same external clock. The high-level

threshold for the external clock is 3.2 V, and the low-level threshold is 0.5 V. The typical duty ratio is

approximately 0.5.

Figure 16 shows a time slice of the two external clock possibilities and the resulting PWM signal. EXT CLK-A is

the continuous clock with no missing pulse and the PWM-A signal could be frequency synchronized anywhere in

the clock stream. The PWM signal is at 1/8 of the EXT CLK-A frequency. EXT CLK-S is the external clock

stream with a missing pulse every 8 cycles. The phasing of the PWM-S is based on the voltage on the PHSEL

pin. For PHSEL grounded, the PWM-S signal is shifted 90 degrees from what would be the falling edge of the

missing pulse as shown in Figure 16.

16

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