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LM1246 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM1246
Description  150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LM1246 Datasheet(HTML) 6 Page - National Semiconductor (TI)

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System Interface Signal Characteristics (Continued)
Unless otherwise noted: T
A = 25˚C, VCC = +5.0V, VIN = 0.7V, VABL =VCC,CL = 8 pF, Video Outputs = 2.0 VP-P. See (Note 7)
for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CLAMP MIN
Minimum High Level Clamp
Pulse Voltage
Video Clamp Functioning
3.0
V
I
CLAMP Low
Clamp Gate Low Input Current
V
23 = 2V
−0.4
µA
I
CLAMP High
Clamp Gate High Input Current
V
23 = 3V
0.4
µA
t
CLAMP-VIDEO
Time from End of Clamp Pulse to
Start of Video
Referenced to Blue, Red and Green
inputs
50
ns
Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Human body model, 100 pF discharged through a 1.5 k
Ω resistor.
Note 5: Input from signal generator: tr,tf < 1 ns.
Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may change when the device is not operated under the listed test conditions.
Note 8: The supply current specified is the quiescent current for VCC and 5V Dig with RL = . Load resistors are not required and are not used in the test circuit,
therefore all the supply current is used by the pre-amp.
Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 VP-P level at the input. All 16 steps equal,
with each at least 100 ns in duration.
Note 10: dt/dVCC = 200*(t5.5V–t4.5V)/ ((t5.5V +t4.5V)) %/V, where: t5.5V is the rise or fall time at VCC = 5.5V, and t4.5V is the rise or fall time at VCC = 4.5V.
Note 11:
∆AV track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to AVC−50% and measured relative to the AV max condition. For example, at AV max the three
amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to AVC−50%. This yields a typical
gain change of 10.0 dB with a tracking change of ±0.2 dB.
Note 12: The ABL input provides smooth decrease in gain over the operational range of 0 dB to −5 dB:
∆AABL = A(VABL =VABL MAX GAIN)– A (VABL =
VABL MIN GAIN). Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.
Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50
Ω).
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at fIN = 10 MHz for VSEP 10 MHz.
Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used
then a longer clamp pulse may be required.
Note 16: Adjust input frequency from 10 MHz (AV max reference level) to the −3 dB corner frequency (f−3 dB).
Note 17: Once the spot killer has been activated, the LM1246 remains in the off state until VCC is cycled (reduced below 0.5V and then restored to 5V).
Hexadecimal and Binary Notation
Hexadecimal numbers appear frequently throughout this
document, representing slave and register addresses, and
register values. These appear in the format “0x...”. For ex-
ample, the slave address for writing the registers of the
LM1246 is hexadecimal BA, written as 0xBA. On the other
hand, binary values, where the individual bit values are
shown, are indicated by a trailing “b”. For example, 0xBA is
equal to 10111010b. A subset of bits within a register is
referred to by the bit numbers in brackets following the
register value. For example, the OSD contrast bits are the
fourth and fifth bits of register 0x8438. Since the first bit is bit
0, the OSD contrast register is 0x8438[4:3].
Register Test Settings
Table 1. Test Settings shows the definitions of the Test
Settings 1–8 referred to in the specifications sections. Each
test setting is a combination of five hexadecimal register
values, Contrast, Gain (Blue, Red, Green) and DC offset.
TABLE 1. Test Settings
Control
No. of Bits
Test Settings
1234
567
8
Contrast
7
0x7F
(Max)
0x00
Min
0x7F
(Max)
0x7F
(Max)
0x40
(50.4%)
0x7F
(Max)
0x7F
(Max)
0x7F
(Max)
B, R, G
Gain
7
0x7F
(Max)
0x7F
(Max)
0x7F
(Max)
Set V
O to
2V
P-P
0x7F
(Max)
0x40
(50.4%)
0x00
(Min)
0x7F
(Max)
DC Offset
3
0x00
(Min)
0x05
0x07
(Max)
0x05
0x05
0x05
0x05
0x05
Compatibility with LM1237 and LM1247
www.national.com
6


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