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TPS2140 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS2140 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 33 page  TPS2140, TPS2141 TPS2150, TPS2151 SLVS399A − JANUARY 2002 − REVISED MAY 2006 10 www.ti.com electrical characteristics over recommended operating junction temperature range, VI(SW_IN) = 3.3 V for TPS2140/50, VI(SW_IN) = 5 V for TPS2141/51, VI(LDO_IN) =5V, all outputs unloaded (unless otherwise noted) (continued) logic section (SW_EN, SW_EN, LDO_EN, ADJ, SW_PG, LDO_PG) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT II(/SW_EN), source VI(/SW_EN) = 0 V 1 5 Logic input current II(SW_EN), sink VI(SW_EN) = 5 V 1 5 µA Logic input current II(LDO_EN) VI(EN_LDO) = 0 V – 5.5 V −1 1 µA VIH_MIN(/SW_EN) 2 Logic input high level VIH_MIN(SW_EN) 2 V Logic input high level VIH_MIN(LDO_EN) 2 V VIL_MAX(/SW_EN) 0.8 Logic input low level VIL_MAX(SW_EN) 0.8 V Logic input low level VIL_MAX(LDO_EN) 0.8 V Floating input voltage VIF(/SW_EN) SW_EN pin is open 2.5 V Floating input voltage VIF(SW_EN) SW_EN pin is open 0.4 V LDO feedback input current II(ADJ) VI(ADJ) = 0 V – 5.5 V −1 1 µA SW_PG sense threshold, VTH_SW TPS2140, TPS2150 Percentage of VI(SW_IN) 85% 88% 90% SW_PG sense threshold, VTH_SW TPS2141, TPS2151 Percentage of VI(SW_IN) 85% 88% 90% LDO_PG sense threshold, VTH_LDO A percentage of output voltage set point VSET, derived from a resistor divider 92% 94% 96% PG hysteresis (all)‡ VTH_HYS 2% 2.5% 3.5% SW_PG rising edge deglitch‡ td_SWPG_rise 1 2.5 ms PG falling edge deglitches times (all)‡ td_PG_fail 50 150 µs SW_PG minimum output high state voltage VOH_MIN(SW_PG) Source current IO(SW_PG) = 1 mA, VI(SW_OUT) > VTH_SW VI(SW_IN) –0.5 SW_PG maximum output low state voltage VOL_MAX(SW_PG) Sink current IO(SW_PG) = 1 mA, VI(SW_OUT) < VTH_SW 0.5 V LDO_PG maximum output low state voltage VOH_MIN(LDO_PG) Sink current IO(SW_PG) = 1 mA, VI(LDO_OUT) < VTH_LDO 0.5 LDO_PG leakage current ILK(LDO_PG) VO(LDO_PG) = 5.5 V 1 µA ‡ Not tested in production. thermal shutdown characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low thermal shutdown Over temperature trip point‡ Switch and/or LDO in current limit 125 137 °C Low thermal shutdown (whole device) Hysteresis‡ Switch and/or LDO in current limit 10 °C High thermal shutdown Over temperature trip point‡ Switch and LDO are not in current limit 155 170 °C High thermal shutdown (whole device) Hysteresis‡ Switch and LDO are not in current limit 10 °C ‡ Not tested in production. |
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