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TPS2074 Datasheet(PDF) 8 Page - Texas Instruments

Part No. TPS2074
Description  FOUR-PORT USB HUB POWER CONTROLLERS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

TPS2074 Datasheet(HTML) 8 Page - Texas Instruments

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TPS2074, TPS2075
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS288A – SEPTEMBER 2000 – REVISED FEBRUARY 2001
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
4.5 V
≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, ENx = 0 V, BP_DIS = 0 V, CL(3.3V_OUT) = 10 µF (unless
otherwise noted)
internal voltage regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage, dc
VI(BP) = 4.25 V to 5.5 V, IO= 5 mA to 100 mA
3.2
3.3
3.4
V
Dropout voltage
IO = 100 mA
0.6
V
Line regulation
VI(BP) = 4.25 V to 5.25 V, IO= 5 mA
0.1
%/v
Load regulation
VI(BP) = 4.25 V,
IO= 5 mA to 100 mA
0.6%
IOS
Short-circuit current limit†
VI(BP) = 4.25 V, 3.3V_OUT connected to GND
0.12
0.2
0.3
A
Pulldown transistor at 3.3V_OUTPUT
VI(3.3V_OUT) = 3.3 V
10
mA
_
(see Note 1)
VI(3.3V_OUT) = 1 V
5
mA
PSRR
Power-supply ripple rejection (see Note 1)
F = 1 kHz, CL(3.3V_OUT)=4.7 µF, ESR=0.25 Ω ,
IO=5 mA, VI(BP)PP=100 mV
40
dB
Low-level trip threshold voltage at PG
2.88
2.94
3
V
Vhys
Hysteresis voltage at PG (see Note 1)
50
100
mV
VOH
High-level output voltage at PG
4.25 V
≤ VI(BP) ≤ 5.25 V, IO = 2 mA
2.4
V
VOL
Low-level output voltage at PG
4.25 V
≤ VI(BP) ≤ 5.25 V, IO = 3.2 mA
0.4
V
Vref
Reference voltage at PG_DLY
1.22
V
Charge current at PG_DLY
3
µA
td
Delay time at PG (see Notes 1 and 2)
CL(PG_DLY) = 0.47 µF
190
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTES:
1. Specified by design, not tested in production.
2. The PG delay time (td) is calculated using the PG_DLY reference voltage and charge current:
t
d +
C
L(PG_DLY)
V
ref
Charge Current
power switch timing requirements
PARAMETER
TEST CONDITIONS†‡
MIN
TYP
MAX
UNIT
t
Turnon time (see Note 1)
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
4.5
ms
ton
Turnon time (see Note 1)
SP to OUTx
switch
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
4.5
ms
t ff
Turnoff time (see Note 1)
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
15
ms
toff
Turnoff time (see Note 1)
SP to OUTx
switch
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
10
ms
t
Rise time output (see Note 1)
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
4
ms
tr
Rise time, output (see Note 1)
SP to OUTx
switch
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
3
ms
tf
Fall time output (see Note 1)
BP to OUTx
switch
VI(BP) = 5 V, VI(SP) = open, TA = 25°C,
CL = 100 µF, RL = 50 Ω
10
ms
tf
Fall time, output (see Note 1)
SP to OUTx
switch
VI(SP) = VI(BP) = 5 V, TA = 25°C,
CL = 100 µF, RL = 10 Ω
3
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
‡ All BP to OUTx , SP to OUTx switches and the internal 3.3-V voltage regulator are loaded to the recommended continuous current rating of
100 mA, 500 mA and 100 mA, respectively, for the static drain-source on-state resistance measurements.
NOTE 1. Specified by design, not tested in production.


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