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OPA2690 Datasheet(PDF) 25 Page - Texas Instruments |
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OPA2690 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 39 page  E = O E NI 2 +(I R ) +4kTR BN S S 2 NG +(I R ) +4kTR NG 2 2 BI F F E = N I R BI F NG E +(I R ) +4kTR + NI BN S S 2 2 + 4kTR F NG 2 R F 1kW ±200mVOutputAdjustment = = 2 - - Power-supply decouplingnotshown. 5kW 5kW 328W 0.1 F m R G 500W V I 20kW 10kW 0.1 F m -5V +5V 1/2 OPA2690 +5V -5V V O V O VI R F R G OPA2690 www.ti.com SBOS238G – JUNE 2002 – REVISED MARCH 2010 The total output spot noise voltage can be computed ±(NG × VOS(MAX)) ± (RF × IOS(MAX)) as the square root of the sum of all squared output = ±(2 × 4.5mV) ± (402 Ω × 1mA) noise voltage contributors. Equation 7 shows the = ±9.4mV – (NG = noninverting signal gain) general form for the output noise voltage using the A fine-scale output offset null, or dc operating point terms shown in Figure 50. adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques eventually (7) reduce to adding a dc current through the feedback Dividing this expression by the noise gain [NG = (1 + resistor. In selecting an offset trim method, one key RF/RG)] will give the equivalent input-referred spot consideration is the impact on the desired signal path noise voltage at the noninverting input, as shown in frequency response. If the signal path is intended to Equation 8. be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the (8) noninverting input may be considered. However, the dc offset voltage on the summing junction will set up Evaluating these two equations for the OPA2690 a dc current back into the source that must be circuit and component values (see Figure 36) gives a considered. Applying an offset adjustment to the total output spot noise voltage of 12.3nV/ √Hz and a inverting op amp input can change the noise gain and total equivalent input spot noise voltage of 6.1nV/ √Hz. frequency response flatness. For a dc-coupled This is including the noise added by the bias current inverting amplifier, Figure 51 shows one example of cancellation resistor (175 Ω) on the noninverting input. an offset adjustment technique that has minimal This total input-referred spot noise voltage is only impact on the signal frequency response. In this slightly higher than the 5.5nV/ √Hz specification for the case, the dc offsetting current is brought into the op amp voltage noise alone. This will be the case as inverting input node through resistor values that are long as the impedances appearing at each op amp much larger than the signal path resistors. This input are limited to the previously recommend ensures that the adjustment circuit has minimal effect maximum value of 300 Ω. Keeping both (RF || RG) and on the loop gain and hence, the frequency response. the noninverting input source impedance less than 300 Ω will satisfy both noise and frequency response flatness considerations. As the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 47 is not required. DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA2690 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically 5mA out of each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. The total output offset voltage may be considerably reduced by matching the dc source resistances appearing at the two inputs. This reduces the output dc error due to the input bias Figure 51. DC-Coupled, Inverting Gain of -2, with currents to the offset current times the feedback Offset Adjustment resistor. Evaluating the configuration of Figure 36, and using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: BLANKSPACE BLANKSPACE Copyright © 2002–2010, Texas Instruments Incorporated 25 Product Folder Link(s): OPA2690 |
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