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OPA2316S Datasheet(PDF) 6 Page - Texas Instruments |
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OPA2316S Datasheet(HTML) 6 Page - Texas Instruments |
6 / 48 page 6 OPA316, OPA2316, OPA2316S, OPA4316 SBOS703E – APRIL 2014 – REVISED JUNE 2016 www.ti.com Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Thermal Information: OPA316 (continued) THERMAL METRIC(1) OPA316 UNIT SOT23 (DBV) SC70 (DCK) 5 PINS 5 PINS (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6.5 Thermal Information: OPA2316 THERMAL METRIC(1) OPA2316 UNIT SO (D) MSOP (DGK) DFN (DRG) 8 PINS 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance(2) 127.2 186.6 56.3 °C/W RθJC(top) Junction-to-case(top) thermal resistance(3) 71.6 78.8 72.2 °C/W RθJB Junction-to-board thermal resistance(4) 68.2 107.9 31 °C/W ψJT Junction-to-top characterization parameter(5) 22 15.5 2.3 °C/W ψJB Junction-to-board characterization parameter(6) 67.6 106.3 21.2 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A 10.9 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6.6 Thermal Information: OPA2316S THERMAL METRIC(1) OPA2316S UNIT MSOP (DGS) RUG (QFN) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance(2) 189.6 158 °C/W RθJC(top) Junction-to-case(top) thermal resistance(3) 73.9 52 °C/W RθJB Junction-to-board thermal resistance(4) 110.7 88 °C/W ψJT Junction-to-top characterization parameter(5) 13.4 1 °C/W ψJB Junction-to-board characterization parameter(6) 109.1 87 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W |
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