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INA3221-Q1 Datasheet(PDF) 22 Page - Texas Instruments

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Part # INA3221-Q1
Description  Current and Voltage Monitor with Programmable Overcurrent Alerts
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221-Q1 Datasheet(HTML) 22 Page - Texas Instruments

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SCL
SDA
t(LOW)
tr
tfCL
t(HDSTA)
t(HDSTA)
t(HDDAT)
t(HIGH)
t(SUSTA)
t(BUF)
S
S
P
P
t(VDDAT)
t(SUSTO)
t(SUDAT)
tfDA
22
INA3221-Q1
SBOS776B – MARCH 2016 – REVISED MARCH 2016
www.ti.com
Product Folder Links: INA3221-Q1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
(1)
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.
A0 = A1 = 0.
Figure 31. Bus Timing
Table 2. Bus Timing Definitions(1)
PARAMETER
FAST MODE
HIGH-SPEED MODE
UNIT
MIN
MAX
MIN
MAX
f(SCL)
SCL operating frequency
0.001
0.4
0.001
2.44
MHz
t(BUF)
Bus free time between stop and start conditions
1300
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
Repeated start condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
ns
t(HDDAT)
Data hold time
0
0
ns
t(VDDAT)
Data valid time
1200
260
ns
t(SUDAT)
Data setup time
100
10
ns
t(LOW)
SCL clock low period
1300
270
ns
t(HIGH)
SCL clock high period
600
60
ns
tfDA
Data fall time
500
150
ns
tfCL
Clock fall time
300
40
ns
tr
Clock rise time
300
40
ns
Clock rise time for SCLK
≤ 100 kHz
1000
ns
8.5.3 SMBus Alert Response
The INA3221-Q1 responds to the SMBus alert response address. The SMBus alert response provides a quick
fault identification for simple slave devices. When an alert occurs, the master broadcasts the alert response slave
address (0001 100) with the R/W bit set high. Following this alert response, any slave devices that generated an
alert identify themselves by acknowledging the alert response, and sending their respective address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
acknowledge, and continues to hold the alert line low until the interrupt is cleared.


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