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TPD4E05U06-Q1, TPD1E05U06-Q1

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SLVSCO7B – AUGUST 2014 – REVISED AUGUST 2016

Product Folder Links: TPD4E05U06-Q1 TPD1E05U06-Q1

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Copyright © 2014–2016, Texas Instruments Incorporated

Feature Description (continued)

7.3.4 IEC 61000-4-5 Surge Protection

The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts

this current to ground.

7.3.5 I/O Capacitance

The capacitance between each I/O pin to ground is 0.5 pF. These capacitances support data rates up to 5 Gbps.

7.3.6 DC Breakdown Voltage

The DC breakdown voltage of each I/O pin is a minimum of 6.4 V. This ensures that sensitive equipment is

protected from surges above the reverse standoff voltage of 5 V.

7.3.7 Ultra-Low Leakage Current

The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.

7.3.8 Low ESD Clamping Voltage

7.3.9 Easy Flow-Through Routing

The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers

flow-through routing, requiring minimal modification to an existing layout.

7.4 Device Functional Modes

internal diode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06-Q1

(usually within 10s of nano-seconds) the devices reverts to passive.