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TLV171IDBVR Datasheet(PDF) 7 Page - Texas Instruments |
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TLV171IDBVR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 38 page 7 TLV171, TLV2171, TLV4171 www.ti.com SBOS783 – SEPTEMBER 2016 Product Folder Links: TLV171 TLV2171 TLV4171 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation sections for additional information. 6.7 Electrical Characteristics at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage TA = 25°C 0.75 ±2.7 mV TA = –40°C to +125°C ±3.0 dVOS/dT Input offset voltage drift TA = –40°C to +125°C 1 µV/°C PSRR Input offset voltage vs power supply VS = 4 V to 36 V, TA = –40°C to +125°C 90 105 dB INPUT BIAS CURRENT IB Input bias current ±10 pA IOS Input offset current ±4 pA NOISE Input voltage noise f = 0.1 Hz to 10 Hz 3 µVPP en Input voltage noise density f = 100 Hz 27 nV/ √Hz f = 1 kHz 16 INPUT VOLTAGE VCM Common-mode voltage range(1) (V–) – 0.1 (V+) – 2 V CMRR Common-mode rejection ratio VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TA = –40°C to +125°C 94 105 dB INPUT IMPEDANCE Differential 100 || 3 MΩ || pF Common-mode 6 || 3 1012 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 36 V, (V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C 94 130 dB FREQUENCY RESPONSE GBP Gain bandwidth product 3.0 MHz SR Slew rate G = +1 1.5 V/µs tS Settling time To 0.1%, VS = ±18 V, G = +1, 10-V step 6 µs To 0.01% (12 bits), VS = ±18 V, G = +1, 10-V step 10 Overload recovery time VIN × gain > VS 2 µs THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO = 3 VRMS 0.0002% |
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