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A1365LKTTN-2-T Datasheet(PDF) 25 Page - Allegro MicroSystems

Part No. A1365LKTTN-2-T
Description  Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A1365LKTTN-2-T Datasheet(HTML) 25 Page - Allegro MicroSystems

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Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
25
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 22: Writing to EEPROM
Figure 23: EEPROM Programming Pulses
Figure 24: Reading from EEPROM or Volatile Memory
Figure 25: CRC Calculation
VCC
Normal Operation
Normal Operation
High
Impedance
EEPROM
Programming
Pulses
VOUT
t
Write
to Register R#
t
WRITE(E)
t
sPULSE(E)
VOUT
t
VCC
Normal Operation
Normal Operation
VOUT
t
t
READ
t
start_read
Read from
Register R#
Read Acknowledge
R#
C1
C0
C2
Input Data
1x 0
1x 1
0x 2
1x 3 = x3 + x + 1
Writing to EEPROM
In order for the external controller to write to non-volatile
EEPROM, a Write command must be transmitted on the VCC
pin. The controller must also send two Programming pulses,
long high-voltage strobes, via the VOUT pin. These strobes are
detected internally, allowing the A1365 to boost the voltage on
the EEPROM gates. The required sequence is shown in figures
22 and 23.
To ensure EEPROM integrity over lifetime, EEPROM should not
be exposed to more than 100 Write cycles.
Reading from EEPROM or Volatile Memory
In order for the external controller to read from EEPROM or
volatile memory, a Read command must be transmitted on
the VCC line. Within time tstart_read, the VOUT line will stop
responding to the magnetic field and the Read Acknowledge
frame will be transmitted on the VOUT line. The Read Acknowl-
edge frame contains Read data.
After the Read Acknowledge frame has been received from the
A1365, the VOUT line resumes normal operation after time
tREAD. The required sequence is shown in Figure 24.
Error Checking
The serial interface uses a cyclic redundancy check (CRC) for
data-bit error checking (synchronization bits are ignored during
the check). The CRC algorithm is based on the polynomial g(x)
= x3 + x + 1, and the calculation is represented graphically in
Figure 25. The trailing 3 bits of a message frame comprise the
CRC token. The CRC is initialized at 111. If the serial interface
receives a command with a CRC error, the command is ignored.


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