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A1365LKTTN-1-T Datasheet(PDF) 30 Page - Allegro MicroSystems |
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A1365LKTTN-1-T Datasheet(HTML) 30 Page - Allegro MicroSystems |
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30 / 32 page 
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator A1365 30 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com EEPROM Cell Organization Programming coefficients are stored in non-volatile EEPROM, which is separate from the digital subsystem, and accessed by the digital subsystem EEPROM Controller module. The EEPROM is organized as 30-bit-wide words, each word is made up of 24 data bits and 6 ECC (Error Checking and Correction) check bits, stored as shown in figure below. External EEPROM Word Bit Sequence; C# – Check Bit, D# – Data Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EEPROM Bit 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Contents C5 C4 C3 C2 C1 C0 D23 D22 D21 D20 D19 D18 D17 D16 D15 EEPROM ECC Errors Bits Name Description 29:26 – No meaning 25:24 ECC 00 = No error 01 = Error detected and message corrected 10 = Uncorrectable error 11 = No meaning 23:0 D[23:0] EEPROM data EEPROM Error Checking and Correction (ECC) Hamming code methodology is implemented for EEPROM checking and correction. The device has ECC enabled after power-up. The device always returns 30 bits. The message received from controller is analyzed by the device EEPROM driver and ECC bits are added. The first 6 received bits from device to controller are dedicated to ECC. Detecting ECC Error If an uncorrectable error has occurred, bits 25:24 are set to 10, the VOUT pin will go to a high-impedance state, and the device will not respond to the applied magnetic field. Output voltage will go to VBRK(HIGH) if a load resistor RL(PULLUP) is connected to VCC or to VBRK(LOW) if a load resistor RL(PULLDWN) is connected to GND. |
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