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A1365LKTTN-1-T Datasheet(PDF) 29 Page - Allegro MicroSystems |
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A1365LKTTN-1-T Datasheet(HTML) 29 Page - Allegro MicroSystems |
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29 / 32 page 
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator A1365 29 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Register Name Address Description r/w Bits Location Customer Read- Only EEPROM FAC_LOT_NUM 0x00* Factory Lot (uses 3rd to 7th digits of the lot number) r/w 16 15:0 WAFER_NUM Factory Wafer (stores up to 64 wafers) r/w 6 21:16 SCRATCH Factory use only r/w 2 23:22 X_DIE_LOC 0x01* 8 bits X die location (accommodates up to 256 die in X) r/w 8 7:0 Y_DIE_LOC 8 bits Y die location (accommodates up to 256 die in Y) r/w 8 15:8 SCRATCH Factory use only r/w 8 23:16 Customer R/W EEPROM SENS_FINE 0x02 Sensitivity r/w 9 8:0 SENS_COARSE Coarse Sensitivity r/w 2 10:9 QVO Quiescent Output Voltage r/w 9 19:11 FACTORY_RES1 Factory use only r/w 1 20 POL Reverses output polarity r/w 1 21 CLAMP_EN Clamp Enable r/w 1 22 EELOCK EEPROM LOCK w 1 23 FLT_THRESH 0x03 Sets the DC Fault Switchpoint, two’s complement DAC profile r/w 6 5:0 FLT_HYST Fault Hysteresis Adjust, [00] = 0 V, [01] = 30 mV, [10] = 60 mV, [11] = 120 mV r/w 2 7:6 FLT_LATCH Enables Fault Latch r/w 1 8 FLT_DIS Disables Fault r/w 1 9 Misc(x) Reserved for factory use; do not change default state r/w 11 20:10 MISC3_1 Factory-reserved (unused) r/w 3 23:21 CUSTOMER_RES 0x04* Customer-reserved r/w 24 23:0 Volatile Memory Customer Debug Register Disable Analog Output 0x10 Sets the output pin to a high-impedance state r/w 1 0 SHADOW_ENABLE Enables register shadowing to bypass shadowed EEPROM registers r/w 1 1 CUSTOMER_ACCESS Customer write access enabled r 1 2 Factory Reserved Reserved for factory use. Do not change default state. r/w 2 4:3 OVERF_FLT 0 = No Over Field Fault 1 = Over Field Fault occurred, clears on read r 1 5 Factory Reserved Reserved for factory use; do not change default state. r/w 2 8:7 VREAD Change EEPROM read voltage for margining; [00] = 1.2 V (default), [01] = 0 V, [10] = 4.3 V, [11] = undefined r/w 2 10:9 – Reserved for factory use (unused) n/a 13 23:11 ACCESS_CODE 0x24 Customer code (not addressable) 30 29:0 *EEPROM registers or bits that are not shadowed. Memory Address Map EEPROM Margining Allegro factory-tests the capacity of each EEPROM bit to retain a “0” or a “1” state. After the user has completed EEPROM programming, the two VREAD bits could be set to “01” to change the EEPROM margin setting. EEPROM registers that were written by the user should be read and compared to the user-programmed value. The procedure should be repeated using VREAD = “10”. It is not mandatory for the user to execute EEPROM Margining. |
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