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A1365LKTTN-1-T Datasheet(PDF) 19 Page - Allegro MicroSystems

Part No. A1365LKTTN-1-T
Description  Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A1365LKTTN-1-T Datasheet(HTML) 19 Page - Allegro MicroSystems

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Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
19
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION
Programming Sensitivity and Quiescent Volt-
age Output
Sensitivity and VOUT(Q) can be adjusted by programming
SENS_FINE and QVO bits, as illustrated in Figures 7 and 8.
Users should not program sensitivity or VOUT(Q) beyond the
maximum or minimum programming ranges specified in the
Operating Characteristics table. Exceeding the specified limits
will cause the sensitivity and VOUT(Q) drift over the temperature
range (ΔSensTC and ΔVOUT(Q)TC) to deteriorate beyond the
specified values.
Programming sensitivity might cause a small drift in VOUT(Q). As
a result, Allegro recommends programming sensitivity first, then
VOUT(Q).
Coarse Sensitivity
Each A1365 variant is programmed to a different coarse sensitiv-
ity setting. Devices are tested, and temperature compensation is
factory-programmed under that specific coarse sensitivity setting.
If the coarse sensitivity setting is changed, by programming
SENS_COARSE bits, Allegro cannot guarantee the specified
sensitivity drift through temperature range limits (ΔSensTC).
Memory-Locking Mechanisms
The A1365 is equipped with two distinct memory-locking
mechanisms:
Default Lock At power-up, all registers of the A1365 are
locked by default. EEPROM and volatile memory cannot be
read or written. To disable Default Lock, a specific 30-bit
customer access code has to be written to address 0x24 within
Access Code Timeout (tACC = 8 ms) from power-up. After
doing so, registers can be accessed. If VCC is power-cycled,
the Default Lock will automatically be re-enabled. This
ensures that during normal operation, memory content will not
be altered due to unwanted glitches on VCC or the output pin.
Lock Bit After EEPROM has been programmed by the user,
the EELOCK bit can be set high and VCC power-cycled to
permanently disable the ability to read or write any register.
This will prevent the ability to disable Default Lock using the
method described above. Note that after the EELOCK bit is
set high and the VCC pin is power-cycled, you will not have
the ability to clear the EELOCK bit or read/write any register.
Figure 9: Device Sensitivity versus SENS_FINE
Programmed Value
Figure 10: Device VOUT(Q) versus QVO
Programmed Value
Mid Range
Sensitivity, Sens (mV/G)
SENS_FINE Code
QVO Code
Quiescent Voltage Output,
VOUT(Q) (mV)
0
511
Max Specified
SensPR
255 256
Min Specified
SensPR
Specified Sensitivity
Programming Range
Mid Range
0
511
Max Specified
VOUT(Q)PR
VOUT(Q)PR
255 256
Min Specified
Specified VOUT(Q)
Programming Range


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