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A1365 Datasheet(PDF) 17 Page - Allegro MicroSystems

Part No. A1365
Description  Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A1365 Datasheet(HTML) 17 Page - Allegro MicroSystems

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Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
17
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VCLP(VCC) / VCLP(5V)
VCC / 5 V
1–
RatERRCLP =
×100% ,


(17)
where VCLP is either VCLP(HIGH) or VCLP(LOW).
Power-On Reset Voltage (VPOR)
On power-up, to initialize to a known state and avoid current
spikes, the A1365 is held in Reset state. The Reset signal is
disabled when VCC reaches VUVLOH and time tPORR has elapsed,
allowing the output voltage to go from a high-impedance state
into normal operation. During power-down, the Reset signal is
enabled when VCC reaches VPORL, causing the output voltage to
go into a high-impedance state. (Note that a detailed description
of POR and UVLO operation can be found in the Functional
Description section).
Power-On Reset Release Time (tPORR)
When VCC rises to VPORH, the Power-On Reset Counter starts.
The A1365 output voltage will transition from a high-impedance
state to normal operation only when the Power-On Reset Counter
has reached tPORR and VCC has exceeded VUVLOH.
Undervoltage Lockout Threshold (VUVLO)
If VCC drops below VUVLOL, the output voltage will be pulled to
GND. If VCC starts rising, the A1365 will come out of this lock
state when VCC reaches VUVLOH.
UVLO Enable/Disable Delay Time (tUVLO)
When a falling VCC reaches VUVLOL, time tUVLOE is required to
engage the Undervoltage Lockout state. When VCC rises above
VUVLOH, time tUVLOD is required to disable UVLO and to have a
valid output voltage.
Output Saturation Voltage (VSAT)
When output voltage clamps are disabled, the output voltage
can swing to a maximum of VSAT(HIGH) and to a minimum of
VSAT(LOW) .
Broken Wire Voltage (VBRK)
If the GND pin is disconnected (broken wire event), output volt-
age will go to VBRK(HIGH) if a load resistor is connected to VCC,
or to VBRK(LOW) if a load resistor is connected to GND.
DC Fault Switchpoint Error (ErrDFS)
The Over Field Fault Switchpoint is user-programmable with a
step size of StepFAULT. DC Fault Switchpoint Error is a deviation
from the user-programmed value that occurs over the operating
temperature range.
DC Fault Switchpoint Symmetry Error
(ErrDFSS)
Writing FLT_THRESH bits sets the DC Fault Switchpoint for
positive and negative magnetic fields as follows:
Positive Field Fault Switchpoint (VFPSP) = Xpos × VCC and
Negative Field Fault Switchpoint (VFNSP) = Xneg × VCC where
Xpos + Xneg = 1. For example, programming VFPSP = 0.8 × VCC
should automatically set VFNSP = 0.2 × VCC. For a measured
VFPSP ,the DC Fault Switchpoint Symmetry error is the delta
between the expected VFNSP and the measured one.
Transient Fault Response Time (tTFR)
The time interval between a) when the input crosses the DC Fault
Switchpoint and b) when the FAULT pin reaches 20% of its final
value.
20
(%)
t
Transient Fault
Response Time
DC Fault
Switchpoint
Applied magnetic Field
Transducer Output
V
FAULT
(t
)
TFR
Figure 7: Transient Fault Response Time (tTFR)


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