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LMH6503 Datasheet(PDF) 16 Page - National Semiconductor (TI) |
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LMH6503 Datasheet(HTML) 16 Page - National Semiconductor (TI) |
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16 / 20 page  Application Information (Continued) NOISE Figure 5 describes the LMH6503’s output-referred spot noise density as a function of frequency with A VMAX = 10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50 Ω, the input noise contribu- tion is minimal. At A VMAX = 10V/V, the LMH6503 has a typical flat-band input-referred spot noise density (e in) of 6.6nV/ . For applications with −3dB BW extending well into the flat-band region, the input RMS voltage noise can be deter- mined from the following single-pole model: (7) CIRCUIT LAYOUT CONSIDERATIONS Good high-frequency operation requires all of the de- coupling capacitors shown in Figure 6 to be placed as close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate ground plane and low inductive power returns are also required of the layout. Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency performance. The parasitic inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load capacitance, C L, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or circuit oscillation. The LMH6503 is fully stable when driving a 100 Ω load. With reduced load (e.g. 1k Ω) there is a possibility of instability at very high frequen- cies beyond 400MHz especially with a capacitive load. When the LMH6503 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100 Ω and 39pF in series tied between the LMH6503 output and ground). C L can also be isolated from the output by placing a small resistor in series with the output (pin 10). Component parasitics also influence high frequency results. Therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. National Semiconductor suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing and characterization: Device Package Evaluation Board Part Number LMH6503MA SOIC-14 CLC730033 LMH6503MT TSSOP-14 CLC730146 The evaluation board is shipped when a device sample request is placed with National Semiconductor. SINGLE SUPPLY OPERATION It is possible to operate the LMH6503 with a single supply. To do so, tie pin 11 (GND) to a potential about mid point between V + and V−. Two examples are shown in Figure 7 & Figure 8. 20073922 FIGURE 5. Output Referred Voltage Noise vs. Frequency 20073957 FIGURE 6. Required Power Supply Decoupling 20073935 FIGURE 7. AC Coupled Single Supply VGA www.national.com 16 |
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