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TNETE2004PAC Datasheet(PDF) 7 Page - Texas Instruments |
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TNETE2004PAC Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 47 page  TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) miscellaneous interface TERMINAL † NAME NO. TYPE† DESCRIPTION NAME 120 128 ATEST 44 50 A Analog test pin. ATEST provides access to the filter of the reference PLL. When operating correctly, ATEST presents a voltage between 1–2 V. CMODE0 CMODE1 47 48 53 54 I Compatibility mode. Eases compatibility with third-party media-access controllers (MACs) (see Table 2). DEVSEL2 DEVSEL3 DEVSEL4 95 96 98 105 106 108 I Device select. DEVSEL2–DEVSEL4 specifies the three most-significant bits of a 5-bit number used to address a PHY on the management-data interface. The two least-significant bits are set as 00, 01, 10, and 11 for PHY0–PHY3, respectively. IREF 43 49 A Current reference. Used to set a current reference for the analog circuitry. IREF must be connected to ground by a 180 ± 5-Ω resistor. MDCLK 99 109 I Management-data clock. MDCLK is used to clock data in and out of the MDIO port. MDIO 100 110 I/O Management-data I/O. MDIO is the serial management-data interface. PWRDWN 54 60 I Power down. When asserted, PWRDWN places all four PHYs in the lower power state. Transmitting and receiving are inhibited in this state. RES1 55 61 O Reserved RESET 15 19 I Global reset. RESET is used to reset all four PHY sections. XTAL1 50 56 A Crystal oscillator pins. Connect a 20-MHz crystal across XTAL1 and GND, or drive XTAL1 from a 20-MHz crystal-oscillator module. XTAL2 51 57 A Connect a 27-pF capacitor across XTAL2 and XTAL1 and connect a 27-pF capacitor between XTAL2 and GND. If a crystal-oscillator module is used, do not connect anything to XTAL2. † A = analog, I = input, O = output, I/O = 3-state input/output JTAG interface TERMINAL ‡ NAME NO. I/O‡ DESCRIPTION NAME 120 128 TCK 36 42 I Test clock. TCK is used to clock state information and test data into and out of the device during operation of the JTAG. TDI 37 43 I Test data input. TDI is used to serially shift test data and test instructions into the device during operation of the JTAG. TDO 38 44 O Test data output. TDO is used to serially shift test data and test instructions out of the device during operation of the JTAG. TMS 40 46 I Test mode select. TMS controls the operating state of the JTAG. TRST 39 45 I Test reset. TRST is used for asynchronous reset of the JTAG controller. ‡ I = input, O = output |
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