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IDT72V293L7PFI Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72V293L7PFI Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 45 page 5 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 to-HIGH transition of WCLK. Similarly, the PAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable Flag Mode (PFM) pin. The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RT input during a rising RCLK edge initiates a retransmitoperationbysettingthereadpointertothefirstlocationofthememory array. A zero-latency retransmit timing mode can be selected using the RetransmittimingModepin(RM).DuringMasterReset,aLOWonRMwillselect zero-latency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Retransmit Timing with zero-latency. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead IW OW Write Port Width Read Port Width L L x18 x18 L H x18 x9 H L x9 x18 H H x9 x9 TABLE 1 — BUS-MATCHING CONFIGURATION MODES outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian ( BE) pin. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then D8isassumedtobeavalidbitandD16andD17areignored.IPmodeisselected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe data written to and read from the FIFO. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are fabricated using IDT’s high speed submicron CMOS technology. |
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