A29L161B datasheet(20/41 Pages) AMICC | 2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory

20 / 41 page

A29L161B Series

(December, 2015, Version 1.0)

AMIC Technology, Corp.

RY/

BY : Read/Busy

The RY/

BY is a dedicated, open-drain output pin that

indicates whether an Embedded algorithm is in progress or

complete. The RY/

BY status is valid after the rising edge of

the final

WE pulse in the command sequence. Since RY/ BY

is an open-drain output, several RY/

BY pins can be tied

together in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing or

programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Suspend

mode), or is in the standby mode.

Table 10 shows the outputs for RY/

BY . Refer to “RESET

Timings”, “Timing Waveforms for Program Operation” and

“Timing Waveforms for Chip/Sector Erase Operation” for

more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program

or Erase algorithm is in progress or complete, or whether the

device has entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after the rising edge

of the final

WE pulse in the command sequence (prior to the

program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause I/O6 to toggle.

(The system may use either

OE or CE to control the read

cycles.) When the operation is complete, I/O6 stops toggling.

After an erase command sequence is written, if all sectors

selected

for

erasing

are

protected,

I/O6

toggles

for

approximately 100

μs, then returns to reading array data. If not

all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use I/O6 and I/O2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), I/O6 toggles. When the device

enters the Erase Suspend mode, I/O6 stops toggling.

However, the system must also use I/O2 to determine which

sectors are erasing or erase-suspended. Alternatively, the

system can use I/O7 (see the subsection on " I/O7 :

Data

Polling").

If a program address falls within a protected sector, I/O6

toggles for approximately 2

μs after the program command

sequence is written, then returns to reading array data.

I/O6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC

Characteristics" section for the timing diagram. The I/O2 vs.

I/O6 figure shows the differences between I/O2 and I/O6 in

graphical form. See also the subsection on " I/O2: Toggle Bit

II".

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final

WE pulse in the command

sequence.

I/O2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either

OE or CE to control the read

cycles.) But I/O2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O6, by comparison,

indicates whether the device is actively erasing, or is in Erase

Suspend, but cannot distinguish which sectors are selected

for erasure. Thus, both status bits are required for sector and

mode information. Refer to Table 10 to compare outputs for

I/O2 and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and

the section " I/O2: Toggle Bit II" explains the algorithm. See

also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O2

vs. I/O6 figure shows the differences between I/O2 and I/O6 in

graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read

I/O7 - I/O0 at least twice in a row to determine whether a

toggle bit is toggling. Typically, a system would note and

store the value of the toggle bit after the first read. After the

second read, the system would compare the new value of the

toggle bit with the first. If the toggle bit is not toggling, the

device has completed the program or erase operation. The

system can read array data on I/O7 - I/O0 on the following

read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of I/O5 is high (see the section

on I/O5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as I/O5 went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and the

system must write the reset command to return to reading

array data.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O5 has not gone high. The

system may continue to monitor the toggle bit and I/O5

through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the

system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figure

6).

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions I/O5 produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

The I/O5 failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to

"0." Only an erase operation can change a "0" back to a "1."

Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, I/O5

produces a "1."

Under both these conditions, the system must issue the reset

command to return the device to reading array data.

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