DS1746/DS1746P

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DATA

ADDRESS

FUNCTION/RANGE

1FFFF

10 YEAR

YEAR

YEAR

00-99

1FFFE

X

X

X

10 MO

MONTH

MONTH

01-12

1FFFD

X

X

10 DATE

DATE

DATE

01-31

1FFFC

BF

FT

X

X

X

DAY

DAY

01-07

1FFFB

X

X

10 HOUR

HOUR

HOUR

00-23

1FFFA

X

10 MINUTES

MINUTES

MINUTES

00-59

1FFF9

OSC

10 SECONDS

SECONDS

SECONDS

00-59

1FFF8

W

R

10 CENTURY

CENTURY

CENTURY

00-39

OSC = STOP BIT

R

= READ BIT

FT = FREQUENCY TEST

W

= WRITE BIT

X

= SEE NOTE BELOW

BF = BATTERY FLAG

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE

(chip enable) is low. The device architecture allows ripple-through access to any of the address locations

stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times

inputs are changed while CE and OE remain valid, output data will remain valid for output data hold

WRITING DATA TO RAM OR CLOCK

The DS1746 is in the write mode whenever WE , and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE , or CE . The addresses must be held valid throughout

typical application, the OE signal will be high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus contention. If OE is low prior to

WE transitioning low the data bus can become active with read data defined by the address inputs. A low