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MSP430FR2111IRLLT Datasheet(PDF) 12 Page - Texas Instruments

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Part No. MSP430FR2111IRLLT
Description  Mixed-Signal Microcontrollers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430FR2111IRLLT Datasheet(HTML) 12 Page - Texas Instruments

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12
MSP430FR2111, MSP430FR2110
SLASE78A – AUGUST 2016 – REVISED AUGUST 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430FR2111 MSP430FR2110
Specifications
Copyright © 2016, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages referenced to VSS.
(3)
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5
Specifications
5.1
Absolute Maximum Ratings
(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC pin to VSS
–0.3
4.1
V
Voltage applied to any pin(2)
–0.3
VCC + 0.3
(4.1 V Max)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, TJ
85
°C
Storage temperature range, Tstg
(3)
–40
125
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.2
ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±250
(1)
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
(2)
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3)
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-1.
(4)
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(5)
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(6)
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
5.3
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage applied at DVCC pin(1) (2)
1.8
3.6
V
VSS
Supply voltage applied at DVSS pin
0
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
85
°C
CDVCC
Recommended capacitor at DVCC
4.7
10
µF
fSYSTEM
Processor frequency (maximum MCLK frequency)(3) (4)
No FRAM wait states
(NWAITSx = 0)
0
8
MHz
With FRAM wait states
(NWAITSx = 1)(5)
0
16(6)
fACLK
Maximum ACLK frequency
40
kHz
fSMCLK
Maximum SMCLK frequency
16(6)
MHz


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