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MSP430FR2111IRLLT Datasheet(PDF) 52 Page - Texas Instruments |
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MSP430FR2111IRLLT Datasheet(HTML) 52 Page - Texas Instruments |
52 / 75 page Q 0 1 D S Edge Select P1IES.x P1IFG.x P1 Interrupt P1IE.x P1IN.x To module P1SEL.x From Module1 P1OUT.x P1DIR.x 11 From Module1 DVCC DVSS P1REN.x EN D Bus Keeper From JTAG To JTAG 2 bit 2 bit 10 01 00 11 10 01 00 From Module2 DVSS From Module2 C0,C1,C2,C3 A0..A7 P1.5/ /TMS/A5 UCA0CLK P1.4/ /TCK/A4 UCA0STE P1.6/ /TB0.1/TDI/TCLK/A6 UCA0RXD/UCA0SOMI P1.7/ /TB0.2/TDO/A7 UCA0TXD/UCA0SIMO /VREF+ P1.1/UCA0CLK/ACLK/C1/A1 P1.0/UCA0STE/SMCLK/C0/A0/Veref+ P1.3/UCA0TXD/UCA0SIMO/C3/A3 P1.2/UCA0RXD/UCA0SOMI/ A2/Veref- TB0TRG/C2/ 1 P1SEL.x= 11 52 MSP430FR2111, MSP430FR2110 SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Detailed Description Copyright © 2016, Texas Instruments Incorporated 6.11.15 Input/Output Diagrams 6.11.15.1 Port P1 Input/Output With Schmitt Trigger Figure 6-1 shows the port diagram. Table 6-34 summarizes the selection of the pin functions. NOTE: Functional representation only. Figure 6-1. Port P1 Input/Output With Schmitt Trigger |
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