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MSP430FR2111IRLLT Datasheet(PDF) 48 Page - Texas Instruments |
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MSP430FR2111IRLLT Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 75 page  48 MSP430FR2111, MSP430FR2110 SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Detailed Description Copyright © 2016, Texas Instruments Incorporated Table 6-21. SYS Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus Error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh System configuration 0 SYSCFG0 20h System configuration 1 SYSCFG1 22h System configuration 2 SYSCFG2 24h System configuration 3 SYSCFG3 26h Table 6-22. CS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET CS control 0 CSCTL0 00h CS control 1 CSCTL1 02h CS control 2 CSCTL2 04h CS control 3 CSCTL3 06h CS control 4 CSCTL4 08h CS control 5 CSCTL5 0Ah CS control 6 CSCTL6 0Ch CS control 7 CSCTL7 0Eh CS control 8 CSCTL8 10h Table 6-23. FRAM Registers (Base Address: 01A0h) REGISTER DESCRIPTION REGISTER OFFSET FRAM control 0 FRCTL0 00h General control 0 GCCTL0 04h General control 1 GCCTL1 06h Table 6-24. CRC Registers (Base Address: 01C0h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h |
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