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MSP430FR2111IRLLT Datasheet(PDF) 39 Page - Texas Instruments |
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MSP430FR2111IRLLT Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 75 page  39 MSP430FR2111, MSP430FR2110 www.ti.com SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Detailed Description Copyright © 2016, Texas Instruments Incorporated The 1.5-V reference is also internally connected to the comparator built-in DAC as reference voltage. DVCC is internally connected to another source of the DAC reference, and both are controlled by the CPDACREFS bit. For more detailed information, see the Comparator chapter of the MSP430FR4xx and MSP430FR2xx Family User's Guide. A 1.2-V reference voltage can be buffered and output to P1.7/TDO/A7/VREF+, when EXTREFEN = 1 in the PMMCTL2 register. ADC channel 7 can also be selected to monitor this voltage. For more detailed information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide. 6.11.2 Clock System (CS) and Clock Distribution The clock system includes a 32-kHz low-frequency oscillator (XT1), an internal very-low-power low- frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with an internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock (MODOSC). The clock system is designed to target cost-effective designs with minimal external components. A fail-safe mechanism is designed for XT1. The clock system module offers the following clock signals. • Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or 128. • Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK. • Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to 40 kHz. All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 and Table 6-8 summarize the clock distribution used in this device. Table 6-7. Clock Distribution CLOCK SOURCE SELECT BITS MCLK SMCLK ACLK MODCLK VLOCLK EXTERNAL PIN Frequency Range DC to 16 MHz DC to 16 MHz DC to 40 kHz 4 MHz 10 kHz CPU N/A Default FRAM N/A Default RAM N/A Default CRC N/A Default I/O N/A Default TB0 TBSSEL 10b 01b 00b (TB0CLK pin) eUSCI_A0 UCSSEL 10b or 11b 01b 00b (UCA0CLK pin) WDT WDTSSEL 00b 01b 10b ADC ADCSSEL 10b or 11b 01b 00b RTC RTCSS 01b 01b 11b |
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