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MSP430FR2111IRLLR Datasheet(PDF) 61 Page - Texas Instruments |
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MSP430FR2111IRLLR Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 75 page  Using an external positive reference Using an external negative reference VEREF- VREF+/VEREF+ + + 100 nF 10 F µ 100 nF 10 F µ DVSS 61 MSP430FR2111, MSP430FR2110 www.ti.com SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Applications, Implementation, and Layout Copyright © 2016, Texas Instruments Incorporated 7.1.6 General Layout Recommendations • Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz Crystal Oscillators for recommended layout guidelines. • Proper bypass capacitors on DVCC, AVCC, and reference pins if used. • Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals. • See Circuit Board Layout Techniques for a detailed discussion of PCB layout considerations. This document is written primarily about op amps, but the guidelines are generally applicable for all mixed- signal applications. • Proper ESD level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines. 7.1.7 Do's and Don'ts During power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. 7.2 Peripheral- and Interface-Specific Design Information 7.2.1 ADC Peripheral 7.2.1.1 Partial Schematic Figure 7-5 shows the recommended decoupling circuit with either an internal or an external voltage reference. Figure 7-5. ADC Grounding and Noise Considerations 7.2.1.2 Design Requirements As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC. The general guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this. In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate analog and digital ground planes with a single-point connection to achieve high accuracy. |
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