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MSP430FR2111IRLLR Datasheet(PDF) 32 Page - Texas Instruments |
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MSP430FR2111IRLLR Datasheet(HTML) 32 Page - Texas Instruments |
32 / 75 page ![]() TEST/SBWTCK 1/fSBW tSU,SBWTDIO tHD,SBWTDIO tSBW,High tSBW,Low RST/NMI/SBWTDIO tValid,SBWTDIO tSBW,EN tSBW,Ret tEN,SBWTDIO 32 MSP430FR2111, MSP430FR2110 SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Specifications Copyright © 2016, Texas Instruments Incorporated 5.13.11 Emulation and Debug Table 5-23 lists the characteristics of the Spy-Bi-Wire interface. (1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. (2) Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function to their application function. This time applies only if the Spy-Bi-Wire mode was selected. Table 5-23. JTAG, Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.0 V, 3.0 V 0 8 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.0 V, 3.0 V 0.028 15 µs tSU,SBWTDIO SBWTDIO setup time (before falling edge of SBWTCK in TMS and TDI slot Spy-Bi-Wire ) 2.0 V, 3.0 V 4 ns tHD,SBWTDIO SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI slot Spy-Bi-Wire ) 2.0 V, 3.0 V 19 ns tValid,SBWTDIO SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot Spy-Bi-Wire ) 2.0 V, 3.0 V 31 ns tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.0 V, 3.0 V 110 µs tSBW,Ret Spy-Bi-Wire return to normal operation time(2) 2.0 V, 3.0 V 15 100 µs Figure 5-16. JTAG Spy-Bi-Wire Timing |
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