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MSP430FR2111IRLLR Datasheet(PDF) 24 Page - Texas Instruments

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Part No. MSP430FR2111IRLLR
Description  Mixed-Signal Microcontrollers
Download  75 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430FR2111IRLLR Datasheet(HTML) 24 Page - Texas Instruments

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MSP430FR2111, MSP430FR2110
SLASE78A – AUGUST 2016 – REVISED AUGUST 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430FR2111 MSP430FR2110
Specifications
Copyright © 2016, Texas Instruments Incorporated
5.13.7 eUSCI
Table 5-13 lists the clock frequency characteristics of the eUSCI in UART mode.
Table 5-13. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
feUSCI
eUSCI input clock frequency
Internal: SMCLK or MODCLK
External: UCLK
Duty cycle = 50% ±10%
2.0 V,
3.0 V
16
MHz
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
2.0 V,
3.0 V
5
MHz
Table 5-14 lists the switching characteristics of the eUSCI in UART mode.
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
Table 5-14. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tt
UART receive deglitch time (1)
UCGLITx = 0
2.0 V,
3.0 V
12
ns
UCGLITx = 1
40
UCGLITx = 2
68
UCGLITx = 3
110
Table 5-15 lists the clock frequency characteristics of the eUSCI in SPI master mode.
Table 5-15. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
feUSCI
eUSCI input clock frequency
Internal: SMCLK or MODCLK
Duty cycle = 50% ±10%
8
MHz
Table 5-16 lists the switching characteristics of the eUSCI in SPI master mode.
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
(3)
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
11 and Figure 5-12.
Table 5-16. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
3.0 V
1
UCxCLK
cycles
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1,
UCMODEx = 01 or 10
3.0 V
1
UCxCLK
cycles
tSU,MI
SOMI input data setup time
2.0 V
53
ns
3.0 V
35
tHD,MI
SOMI input data hold time
2.0 V
0
ns
3.0 V
0
tVALID,MO
SIMO output data valid time(2)
UCLK edge to SIMO valid,
CL = 20 pF
2.0 V
20
ns
3.0 V
20
tHD,MO
SIMO output data hold time(3)
CL = 20 pF
2.0 V
0
ns
3.0 V
0


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