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MSP430FR2111IRLLR Datasheet(PDF) 16 Page - Texas Instruments |
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MSP430FR2111IRLLR Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 75 page  VBOR VSVS– VSVS+ t V Power Cycle Reset SVS Reset BOR Reset tBOR 16 MSP430FR2111, MSP430FR2110 SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Specifications Copyright © 2016, Texas Instruments Incorporated (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 5.12 Thermal Resistance Characteristics PARAMETERS VALUE UNIT RθJA Junction-to-ambient thermal resistance, still air(1) QFN 24 pin (RLL) 38.7 ºC/W TSSOP 16 pin (PW16) 106.5 RθJC Junction-to-case (top) thermal resistance(2) QFN 24 pin (RLL) 39.5 ºC/W TSSOP 16 pin (PW16) 41.2 RθJB Junction-to-board thermal resistance(3) QFN 24 pin (RLL) 8.6 ºC/W TSSOP 16 pin (PW16) 51.5 5.13 Timing and Switching Characteristics 5.13.1 Power Supply Sequencing Figure 5-5 shows the power cycle, SVS, and BOR reset conditions. Figure 5-5. Power Cycle, SVS, and BOR Reset Conditions Table 5-1 lists the characteristics of the SVS and BOR. (1) A safe BOR can only be correctly generated only if DVCC must drop below this voltage before it rises. (2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+. Table 5-1. PMM, SVS and BOR over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBOR, safe Safe BOR power-down level(1) 0.1 V tBOR, safe Safe BOR reset delay(2) 10 ms ISVSH,AM SVSH current consumption, active mode VCC = 3.6 V 1.5 µA ISVSH,LPM SVSH current consumption, low-power modes VCC = 3.6 V 240 nA VSVSH- SVSH power-down level 1.71 1.81 1.86 V VSVSH+ SVSH power-up level 1.74 1.88 1.99 V VSVSH_hys SVSH hysteresis 80 mV tPD,SVSH, AM SVSH propagation delay, active mode 10 µs tPD,SVSH, LPM SVSH propagation delay, low-power modes 100 µs |
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