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MSP430FR2111IPW16 Datasheet(PDF) 44 Page - Texas Instruments |
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MSP430FR2111IPW16 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 75 page  44 MSP430FR2111, MSP430FR2110 SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Detailed Description Copyright © 2016, Texas Instruments Incorporated Table 6-13 summarizes the selection of the Timer_B high-impedance trigger. (1) When TB0 is set to PWM output function, both port groups can receive the output, and the output is controlled by only the PxSEL.y bits. Table 6-13. TBxOUTH TB0TRGSEL TB0OUTH TRIGGER SOURCE SELECTION Timer_B PAD OUTPUT HIGH IMPEDANCE TB0TRGSEL = 0 eCOMP0 output (internal) P1.6, P1.7, P2.0, P2.1(1) TB0TRGSEL= 1 P1.2 6.11.9 Backup Memory (BAKMEM) The BAKMEM supports data retention functionality during LPM3.5 mode. This device provides up to 32 bytes that are retained during LPM3.5. 6.11.10 Real-Time Clock (RTC) Counter The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5. This module may periodically wake up the CPU from LPM0, LPM3, LPM4, or LPM3.5 based on timing from a low-power clock source such as XT1, ACLK, or VLO. In AM, RTC can be driven by SMCLK to generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to the RTC; however, only one of them can be selected at any given time. The RTC overflow events trigger: • Timer0_B3 CCR0A • ADC conversion trigger when ADCSHSx bits are set as 01b 6.11.11 10-Bit Analog-to-Digital Converter (ADC) The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags. |
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