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MSP430FR2111IPW16 Datasheet(PDF) 33 Page - Texas Instruments |
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MSP430FR2111IPW16 Datasheet(HTML) 33 Page - Texas Instruments |
33 / 75 page TCK 1/fTCK tSU,TMS tHD,TMS tTCK,High tTCK,Low TEST tJTAG,Ret TMS TDO tZ-Valid,TDO tValid,TDO tValid-Z,TDO tSU,TDI tHD,TDI TDI (or TDO as TDI) 33 MSP430FR2111, MSP430FR2110 www.ti.com SLASE78A – AUGUST 2016 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 Specifications Copyright © 2016, Texas Instruments Incorporated Table 5-24 lists the characteristics of the 4-wire JTAG interface. (1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. Table 5-24. JTAG, 4-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17) PARAMETER VCC MIN TYP MAX UNIT fTCK TCK input frequency (1) 2.0 V, 3.0 V 0 10 MHz tTCK,Low TCK low clock pulse duration 2.0 V, 3.0 V 15 ns tTCK,high TCK high clock pulse duration 2.0 V, 3.0 V 15 ns tSU,TMS TMS setup time (before rising edge of TCK) 2.0 V, 3.0 V 11 ns tHD,TMS TMS hold time (after rising edge of TCK) 2.0 V, 3.0 V 3 ns tSU,TDI TDI setup time (before rising edge of TCK) 2.0 V, 3.0 V 13 ns tHD,TDI TDI hold time (after rising edge of TCK) 2.0 V, 3.0 V 5 ns tz-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK) 2.0 V, 3.0 V 26 ns tValid,TDO TDO to new valid output time (after falling edge of TCK) 2.0 V, 3.0 V 26 ns tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK) 2.0 V, 3.0 V 26 ns tJTAG,Ret JTAG return to normal operation time 15 100 µs Rinternal Internal pulldown resistance on TEST 2.0 V, 3.0 V 20 35 50 k Ω Figure 5-17. JTAG 4-Wire Timing |
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