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IDT72V223L15BC Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72V223L15BC Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 45 page 4 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FFfunctionsareselectedinIDTStandardmode.TheIRandORfunctionsare selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory.Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial.Eightdefaultoffsetsettingsarealso provided, so that PAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary.Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. Forserialprogramming, SENtogetherwithLDoneachrisingedgeofWCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WENtogetherwith LD oneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serial or parallel offset loading has been selected. During Master Reset ( MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing beforePartialResetremainunchanged.Theflagsareupdatedaccordingtothe timing mode and offsets in effect. PRS is useful for resetting a device in mid- operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmodeofthe PAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAEand PAFflags. If asynchronous PAE/PAF configuration is selected, the PAEis asserted LOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGHontheLOW- DESCRIPTION (CONTINUED) MASTER RESET ( MRS) READ CLOCK (RCLK/RD*) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK/WR*) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 4666 drw03 HALF-FULL FLAG ( HF) SERIAL ENABLE( SEN) INPUT WIDTH (IW) OUTPUT WIDTH (OW) BIG-ENDIAN/LITTLE-ENDIAN ( BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) BUS- MATCHING (BM) SERIAL CLOCK (SCLK) (x9 or x18) DATA OUT (Q0 - Qn) (x9 or x18) DATA IN (D0 - Dn) IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 Figure 1. Single Device Configuration Signal Flow Diagram |
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