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TNETV1002IDZHK Datasheet(PDF) 22 Page - Texas Instruments |
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TNETV1002IDZHK Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 102 page  DSP Subsystem Functional Overview 12 June 2001 -- Revised December 2002 SPRS180C 3 DSP Subsystem Functional Overview The DSP subsystem is based on the TMS320C54x™ DSP core, on-chip memories and peripherals, and is code-compatible with other C54x products. The following description of the 5471 DSP subsystem is based on Figure 3--1. 8K × 16 Prog RAM 8K × 16 Prog RAM 8K × 16 Prog RAM 8K × 16 Prog RAM C54x™ DSP DMA McBSP TIMER McBSP 8K × 16 Data RAM 8K × 16 Prog RAM API PLL XIO External DSP Memory CODEC CODEC DSP Subsystem 8K × 16 Data RAM 8K × 16 Data RAM 8K × 16 Data RAM MCU Subsystem Figure 3--1. 5471 DSP Subsystem Functional Block Diagram 3.1 DSP Core The 5471 DSP subsystem’s fixed-point, digital signal processor (DSP) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the 5471 DSP subsystem includes the control mechanisms to manage repeated operations, function calls, and DSP interrupts. The DSP core includes the following features: • Low-power C54x™ DSP CPU, operating at up to 100 MHz • Software-programmable wait-state generator with bank-switching wait-state logic • External memory interface -- Program space -- Data space -- I/O space • Scan-based emulation logic |
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